The news #
China’s ChangXin Memory Technologies (CXMT) announced on August 29, 2026 that its LPDDR6 memory has entered mass production - the first commercial deployment of the standard anywhere, and the first time any memory maker beat Samsung and SK Hynix to market on a leading-edge DRAM generation. The first customer is Xiaomi: LPDDR6 debuts in the Xiaomi 18 Fold foldable launching in September 2026, paired with Xiaomi’s in-house XRING O3 3nm chipset, and CEO Lei Jun publicly congratulated CXMT. The parts follow JEDEC’s JESD209-6 spec (published July 2025) with 16Gb dies in a package-on-package design carrying on-die ECC.
Why local AI cares about a phone memory spec #
LPDDR is a phone-first standard, but it is also the standard behind every unified-memory box this site talks about: the DGX Spark’s 273 GB/s, Strix Halo’s 256 GB/s, and the memory in Apple-cousin designs all descend from the same LPDDR families. And decode throughput on an LLM is almost perfectly bandwidth-bound - tok/s tracks memory bandwidth, which is why our benchmark pages lead with GB/s.
The spec-level numbers:
| Generation | Per-pin rate | Note |
|---|---|---|
| LPDDR5X (today) | up to 10.667 Gbps | Spark-class boxes run ~9.4 Gbps on a 256-bit bus to get 273 GB/s |
| LPDDR6 (CXMT) | 12.8 Gbps | JEDEC JESD209-6; about 20% over the LPDDR5X ceiling |
| LPDDR6 (SK Hynix, planned) | 14.4 Gbps | development completed March 2026 on the 1c node; supply planned for H2 2026 |
Two honest caveats before anyone extrapolates. First, per-pin speed is not bandwidth - bandwidth is per-pin speed times bus width, and the controller decides how close a real product gets to the JEDEC ceiling. Strix Halo’s LPDDR5X runs at 8000 Mbps on its 256-bit bus for 256 GB/s, well below the 10.667 ceiling; if its successor holds the same bus width and actually runs LPDDR6 at 12.8 Gbps, the theoretical ceiling moves from roughly 256 GB/s to roughly 409 GB/s, and dense-model tok/s would track that almost linearly. Second, LPDDR6’s dual 12-DQ sub-channels and DVFSL power management help efficiency and capacity scaling more than they help peak bandwidth - the headline gain is still the per-pin number.
The supply-chain angle, briefly #
A Chinese memory company being first to market on a new DRAM generation is a supply-chain event, not just a benchmark one. CXMT reported H1 2026 revenue of 150.31 billion yuan (up 873% year over year) with LPDDR now the core of its business, and it is separately suing the US Defense Department over its January 2025 “military company” designation. The memory behind cheap local-AI boxes has so far come from three Korean and American-adjacent suppliers; a fourth, domestically anchored source changes the pricing and availability picture for the same reason export-control moves around open weights changed the software picture: policy now reaches into the bill of materials.
What it means for buyers #
Do not buy on this news yet. Phone flagships get LPDDR6 first (the Xiaomi 18 Fold, September 2026); unified-memory PCs and mini-PCs follow on SoC timelines, realistically 2027, and only when an SoC vendor wires up the controller to actually run the faster pins. Apple, notably, stays on its own LPDDR path and ships the fastest unified memory in the consumer class regardless - the M5 Ultra’s 1.2 TB/s is further ahead than any LPDDR6 phone part will be.
What the standard does set is the ceiling for the next generation of affordable bandwidth. If LPDDR6 lands in a 256-bit-class mini-PC at real controller rates somewhere north of 10 Gbps, the cheapest 256-512GB boxes of 2027 gain tens of GB/s - and with it, proportionally more tok/s on the open-weight models in the catalog. When those SoCs ship, our benchmarks will measure them the same way we did the Spark’s: real runs, not spec sheets. Until then, the rig finder and the hardware catalog stay the honest answer to what to buy today.