Founder Faraj Aalaei says ACI compresses months of front-end work into days; its public evidence remains company and customer benchmarks.
By [RuntimeWire Staff](/author/runtimewire-staff)
· Published
Primary source: [Forbes](https://www.forbes.com/sites/karlfreund/2026/09/14/cognichip-creates-physics-informed-ai-models-to-speed-chip-design/)
Why it matters #
A credible model-first design system could shorten custom-silicon cycles and expand who can afford them. Production results will determine whether Cognichip's benchmark gains survive tape-out.
Faraj Aalaei, the two-time semiconductor CEO behind Cognichip, unveiled an enterprise chip-design system built around physics-informed AI models, betting that semiconductor expertise belongs inside the model rather than patched together through prompts and general-purpose coding agents.
The September 14th report from Forbes describes Artificial Chip Intelligence, or ACI, as a full-stack system spanning microarchitecture, RTL design, functional verification, power-performance-area optimization and FPGA implementation. Cognichip plans to show additional details at the AI Infra Summit in Santa Clara, which runs from September 15th through September 17th.
For Aalaei, Cognichip is a third run at building a semiconductor company. He previously founded and led Centillium Communications and Aquantia through public listings. Marvell later acquired Aquantia, and Aalaei went on to oversee Marvell's networking and automotive segment. He argued that rising development costs and falling venture investment were draining new-company formation from the chip industry, then founded Cognichip in 2024 after advances in generative AI made a different design workflow plausible. Aalaei recruited co-founders whose backgrounds cover both sides of that thesis. Ehsan Kamalinejad, Cognichip's CTO, earned a Ph.D. in applied mathematics from the University of Toronto and worked on machine learning at Apple and Amazon. Chief architect Simon Sabato previously held chip and systems roles at Google, Cisco and Cadence.
Put the chip knowledge inside the model
Chip-design data presents an unusually difficult training problem. Semiconductor businesses closely guard design files, verification results and manufacturing constraints. The public corpus is thin compared with the software repositories available to train coding models.
Cognichip says it addressed that shortage by pairing experienced chip designers with AI researchers. The designers produced and curated domain data, while the researchers generated synthetic examples and built models grounded in logic, timing, power and physical constraints. ACI also supports customer-controlled data and deployment configurations intended to keep sensitive intellectual property inside customer firewalls.
The distinction Cognichip draws against agentic competitors requires some precision. ACI Enterprise includes an agent framework for orchestrating tools and tasks. Cognichip's argument is that the underlying models already understand hardware abstractions and physical constraints, leaving the agents to coordinate work rather than compensate for a general-purpose model that treats RTL as another programming language.
Cognichip is also extending ACI into field-programmable gate arrays, or FPGAs, where shorter implementation cycles could matter for robotics, automotive systems and industrial equipment. Forbes says ACI can move an FPGA concept to working code in a few hours.
The 100x claim needs a denominator
Forbes reports that early ACI results point to a roughly 100x chip-design speedup. Manoher Bommena, a Renesas vice president of engineering, said the system "simply 'speaks chip.'" Those assessments give Cognichip useful industry validation, though the published figures do not yet share one consistent benchmark.
Forbes reports that one engineer used ACI to process a 55-page specification in a few days, compared with the roughly four to five months Cognichip says comparable work would normally require. The work included microarchitecture, RTL design, functional verification and power-performance-area optimization. The report does not provide a published methodology, baseline staffing model or independent replication that would reconcile this example with the roughly 100x headline claim.
A production tape-out would provide a harder test. In April, TechCrunch reported that Cognichip's evidence centered on collaborations and demonstrations rather than an identified chip designed through ACI. The latest materials add broader workflows and more evaluation data, while the case for ACI still rests on Cognichip's measurements and customer testimony.
That proof burden is higher in semiconductor design than in software generation. Incorrect application code can often be patched after deployment. A design flaw discovered after tape-out can force months of delay and an expensive respin. Chipmakers will judge ACI on verification coverage, manufacturability and production silicon alongside raw generation speed.
Aalaei has $93M to make the case
Cognichip has raised $93 million since its founding. A $33 million seed round announced in May 2025 was co-led by Mayfield and Lux Capital, with FPV Ventures and Candou Ventures participating. TechCrunch reported in 2025 that Aalaei founded Candou Ventures in 2016, giving Cognichip a founder-linked investor alongside its institutional backers.
In April 2026, Cognichip announced a $60 million Series A led by Seligman Ventures. SBI Investment joined, and the seed investors participated again. Intel CEO Lip-Bu Tan and Seligman managing partner Umesh Padval joined Cognichip's board.
Capital is arriving quickly across AI chip-design software. Ricursive Intelligence raised $300 million at a $4 billion post-money valuation in January. ChipAgents, Agentrys and Astrus are building their own AI-assisted design systems, while Synopsys, Cadence and Siemens already control the established electronic-design automation workflows that semiconductor engineers use.
Cognichip's opening is the industry's dissatisfaction with incremental automation. Aalaei is asking chipmakers to place a purpose-built model near the center of their design process. The conference demonstrations can establish that ACI works quickly. Production silicon will determine whether his third semiconductor company has changed how chips get built.