SAN FRANCISCO – AMD is looking to tighten its grip on the AI processor market with the all-new Venice series.
Showcased at the vendor’s Advancing AI event, CEO Lisa Su said rising compute demands and shifts to agentic AI are driving projections that the AI accelerator market will reach around $1.4 trillion by 2030.
“That means by the end of the decade, the AI accelerator market is going to approach the size of the entire semiconductor market today,” Su said during her keynote.
After being crowned by Gartner as the company to beat for server central processing units (CPUs), AMD came out to defend its title with the sixth-generation 9006 Series EPYC line, which is set to roll out later this year.
A press briefing prior to Su’s keynote saw Ravi Kuppuswamy, SVP and GM of AMD’s server product and engineering, claim Venice provides 2.2-times better throughput than Nvidia’s upcoming Vera challenger line, adding: “Right out of issue, we have a 20% advantage, and we have not even finished completed tuning.”
Su used her keynote to tout the company’s mastery of the CPU, with AMD projecting the server CPU market to grow by more than 50% to more than $200 billion by 2030, compared to just $25 billion today, with agentic demand driving that leap. And Su said that every customer conversation around agentic buildout is “just beginning.”
“Last year we thought it might grow, let's call it 18 to 20% CAGR [compound annual growth rate] to an overall market size of $60 billion,” the CEO claimed. “But frankly, what we're seeing is that the rate and pace of agentic AI adoption is much, much faster than any of us thought. We're talking about agents going from millions to billions, like we're able to increase all of our productivity, and that requires a tremendous amount of CPU infrastructure.”
AMD’s new Venice line sits at the heart of another update from Advancing AI, Helios, the chip giant’s rack-scale platform set to rival Nvidia’s NVL72. AMD's Salina 400 Gb/s (400G) data processing unit manages the Helios front-end network, off infrastructure tasks from Venice to free up valuable cores and improve agentic performance.
The initial Venice lineup will eventually be supported by Venice-X, a specialized, cache-heavy variant of the standard sixth-generation launching in 2027.
“For us, one architecture spans dozens of different chips, and that breadth is something that no other CPU vendor can match,” Su proclaimed.