AMD said it has achieved an estimated 4x increase in AI energy efficiency from 2024 to mid-2026, exceeding its projected 3x target for the period. It is working toward a 20x improvement in rack-scale AI training and inference efficiency by 2030, a goal it set in June 2025.
The company measures progress against a 2024 baseline using performance-per-watt metrics across representative AMD rack configurations. AMD noted that its 2026 results combine measured product data with modeled estimates where final performance data were unavailable. When AMD set the 20x goal, it said the target itself outpaced the industry improvement trend from 2018 to 2025 by nearly 3x; the interim 4x result lands ahead of even that accelerated slope.
Rack-Scale, Not Component-Level #
AMD’s 20×30 initiative targets rack-scale gains rather than component-level improvements alone. The company is positioning its approach around coordinated advances across compute silicon, process technology, memory and interconnect bandwidth, software, and system design. This reflects the growing importance of full-stack optimization as AI infrastructure shifts from individual accelerators to densely integrated racks. “The next wave of AI efficiency will depend on tighter co-optimization across compute silicon, memory, interconnects, software and rack-scale system design,” said Sam Naffziger, AMD senior vice president and Corporate Fellow, in the announcement. It is the same full-stack pitch behind Lux, the AMD-powered system that became the first Genesis Mission supercomputer at Oak Ridge National Laboratory.
The company expects higher energy efficiency to provide two outcomes by 2030, depending on how customers deploy the available performance. Under one scenario, AMD projects that approximately two future racks could deliver the same compute capability as 570 racks from 2024, reducing use-phase electricity consumption by 20x and carbon intensity by 28x. Alternatively, the projected improvements could enable 20x more compute, measured in floating-point operations per second per watt, with the same energy use.
Memory and interconnect technologies are central to that effort. AMD identified high-bandwidth memory, larger caches, and tighter memory-to-compute integration as mechanisms to keep compute resources fed while reducing energy-intensive data movement. High-speed scale-up interconnects, the fabric at the center of AMD’s 72-GPU MI455X Helios rack, are also expected to become increasingly important as larger AI workloads require more efficient communication among GPUs, CPUs, memory, and other rack-level components.
Software Could Push It to 100x #
Software remains another component of the company’s efficiency strategy. AMD said its ROCm software stack, open standards, and customer optimization efforts are intended to improve AI training and inference throughput while reducing energy use per generated token. The company expects software, algorithmic, and model-level advances to compound hardware and systems gains, potentially supporting up to a 100x overall improvement in AI energy efficiency by 2030.
The focus is increasingly on useful compute per available watt. As power delivery, cooling capacity, and physical infrastructure become constraints on AI expansion, improvements in rack-scale performance per watt could reduce electricity use and improve infrastructure utilization without requiring power consumption to scale linearly with compute demand.