This is E. Yoon's submission for the Chips and AI Hackathon.
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Introduction
We demonstrate an LLM agent autonomously realizing the physical layout for complex analog, mixed-signal, and digital integrated circuits, starting from schematics to a DRC-clean GDS ready for tapeout.
Video Demos
Analog — 5T Op-Amp
Mixed-Signal — CML Differential Pair
Digital — 8-core DDS + 8:1 SerDes Power Routing
W/L tuning
The most impactful demo, in my opinion, is not the autonomous routing, but the ability to command the agent to execute layout actions using intelligent natural language.
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Motivation
To manufacture a chip, you don't send the foundry the chip’s schematics or RTL files. Instead, you send the GDS mask set, a 2D CAD drawing specifying the polygon shapes for each process layer.
Physical design is the process of turning a symbolic circuit description into the actual, material realization of the circuit. For example, a MOS transistor is formed where a polysilicon layer crosses over an active diffusion region.
The final GDS mask ultimately determines the chip's correctness and performance — a schematic with excellent simulation results could fail due to unaccounted layout parasitics; an RTL could even be physically unroutable due to congestion — yet stock autoregressive LLMs struggle precisely at this final physical layer, where circuit behavior becomes a function of spatial geometry.
Why does an LLM easily generate SystemVerilog code, but even OpenAI’s latest and greatest Astra 6 can't lay out a simple current mirror?
This clip shows stock Astra 6 failing to route a simple current mirror circuit without DRC errors, even with manual intervention (notwithstanding the bad placement, which I had already given up on).
Naively serializing a raw GDS file causes the agent's context to be filled with arbitrary numerical variations of a million polygon XY coordinates, shown in this agent reasoning trace from a failed training run:
A layout decision depends on spatial relations: which shapes are near, which edges align, and where there is clearance. These relations are deeply implicit in a tokenized GDS:
- Invariants: Two identical layouts translated by (+1 µm, −2 µm) produce completely different token streams.
- Position doesn't help : Serializing a layout imposes a 1D order on 2D geometry, and no order keeps every spatial neighbor close in the sequence. Positional encodings bias attention toward nearby tokens, which here are often not spatial neighbors.
- Content doesn't help : Attention compares token embeddings, which encode lexical identity, not numeric closeness. 1200 matches 1200, but a 0.14 µm clearance (1200 vs. 1214) has no signal to attend to. The token
x_B − x_Aisn't in the input. - Explicit reasoning : An agent can be told to subtract two coordinates, with an O(n²) penalty. Our logs show the agent fixating on local coordinate arithmetic but failing to recognize the overall grid formation.
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Method
We discuss the custom harness that enabled generic coding agents to lay out complex IC designs.
Contribution 1: Representation space
We engineers recognize a CMOS inverter by seeing a PMOS above an NMOS. Inspired by how engineers reason about layout, we construct a relational representation space:
- A layout object is a directed hypergraph.
- Nodes are the circuit devices (e.g. transistors, resistors, capacitors).
- Each hyperedge connects a set of devices to another set under some relational operator.
- Nodes can be arbitrarily grouped and ungrouped to be transformed together in a single operation.
Instead of editing XY coordinates, the model action space is restricted to discrete relational operators:
mirror = group(M1, M2)
diff_pair = group(M3, M4)
tail = M5
above(mirror, diff_pair)
above(diff_pair, tail)
align_center_x(mirror, diff_pair, tail)
amplifier = group(mirror, diff_pair, tail)
like above(MOS1, MOS2) or left_of(MOS1, MOS2). Thus spatial relationships are expressed invariantly.
Each relation addresses whole groups. Moving mirror preserves its internal arrangement; grouping the three stages makes the amplifier available as a single object for subsequent edits.
$$ \operatorname{above}(A,B) \quad\Longrightarrow\quad y_{\min}(A);\geq;y_{\max}(B)+s_{AB} $$ Here, $y_{\min}(A)$ is the bottom edge of group A, $y_{\max}(B)$ is the top edge of group B, and $s_{AB}$ is the required separation. The post processing geometry engine resolves coordinates using the device dimensions and spacing requirements.
Analog constraints such as symmetry, matching, common-centroid, and abutment are relations to begin with. This representation makes relations first-class hyperedges. It also reduces the number of actions; for example, moving a differential pair is one action instead of many correlated ones. Shorter action sequences are easier to learn, and nesting groups lets the agent compose increasingly complex structures from learned primitives.
Moreover, human natural-language translates extremely well to precise but intuitive layout edits; for example, "put mirror group A above the diff pair group B, both symmetric about the tail source group C", which encourages human feedback in the loop.
Our representation space lets LLMs reason about spatial relationships token-efficiently. The key connection is that self-attention scores pairwise interactions between tokens, and our representation translates implicit spatial relationships in coordinates into explicit object-relational form, forcing the spatial relationships to be scored in attention computation.
Explicit relation tokens make layout intent available to the model without requiring it to reconstruct that intent from raw polygon coordinates.
The relative action space also structurally minimizes DRC errors, since the parameterized locations can later be tuned to the minimum gap allowed by the PDK. Conversely, different W/Ls can be adjusted automatically after laying out once.
Collision in the final stage is not significant since devices are usually similar in W/L size. However, the allowed gap can always be directly computed and adjusted.
Contribution 2: Placement skill
The second contribution is a reusable "device placement skill" for LLM agents. This skill enables an agent to generate a sensible, tight initial placement solution in one shot; the engineer can further iterate on the initial solution because it lives in the relative space from above. The greatest advantage is probably that the skill allows engineers to execute low-level geometric edits with high-level, intelligent natural language.
Circuit automorphisms (swaps) reveal subcircuits that occupy equivalent structural roles. We identify symmetric subcircuits to learn useful relationships: for example, VDD biased PMOS row, PMOS+NMOS CMOS pair, differential pairs, common centroids.
These are the graph cuts identified autonomously by the agent for the CML differential pair.
The skill enables an agent to identify symmetry-equivalent devices, then use bottom-up hierarchical grouping (start with small groups, merge them into larger groups, then repeat) to find whatever groups it considers useful. There is no single way to identify a useful group.
choose a relationship to inspect → propose memberships using terminal patterns → check those patterns → compute complete interfaces → use the result to inform a placement decision.
Repeat:
Build the hypergraph between the current groups.
Propose groups that together form a larger function.
Inspect each proposal’s internal and boundary connections.
Accept useful merges.
Replace their children with a parent group.
Contribution 3: Routing skill
The third contribution is the routing skill. Good placement usually results in good routing, so the routing skill is a simple skill that instructs the agent to plan and make connections between node terminals until the graph equals the original schematic's connectivity graph (LVS check).
AddWire(
net="out",
layer="M1",
start=TerminalRef("M1.D"),
end=TerminalRef("M2.D"),
points=path,
width=width,
)
A route is defined as a metal rectangle between terminals; a bent route is formed by connecting two terminals of two routes, which can also be grouped. The skill could be extended in the future to optimize for metal types, or better resolve layer planning.
This is a long-horizon routing task that completes power and signal routes between parallel digital IP macros until LVS is green:
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Conclusion
We recast physical layout from geometric coordinate space into a symbolic relational space, so the spatial relationships between devices that drive electrical circuit behavior become explicit to transformer self-attention. Layout state is a directed hypergraph whose nodes are devices and whose hyperedges assert relative spatial relations (left_of, above) between arbitrary groupings of devices. This (1) replaces absolute coordinates with relational operators, and (2) lets an arbitrary group of devices be addressed and transformed as a single unit; because groups can nest, actions compose hierarchically. A custom placement and routing skill builds on this framework to form the agent harness. Our harness enables both the LLM and the human designer to reason and interoperate on IC physical design.