RTLLM

Researchers introduced HORIZON, a self-evolving agent framework that treats hardware design as repository-level code evolution, achieving 100% benchmark completion across ChipBench, RTLLM, Verilog-Eva…

Researchers have developed TTT-RTL, the first per-design test-time training framework that uses reinforcement learning to optimize hardware designs generated by large language models. The system close…

Researchers have developed CPPL, a compiler-mediated hardware design framework that converts large language model-assisted circuit generation into a statically checkable frontend problem. The system c…