01:03
2026-07-22
arxiv.org
artificial-intelligence
SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor
Researchers have developed SEAM-V, a hybrid-decoupled vector execution architecture for RISC-V Vector Extension (RVV) that achieves a geometric-mean speedup of 1.34x across 17 representative kernels c…