AI hardware news — GPUs, TPUs, custom AI chips, NVIDIA, AMD, Intel, and the infrastructure powering large-scale model training and inference.
The Nvidia GB10, a collaboration with MediaTek, integrates a Blackwell GPU with 48 SMs and a powerful CPU consisting of 10 Cortex X925 and 10 Cortex A725 cores. The memory subsystem features a split L3 cache design (8 MB…
The Intel 8087 floating-point coprocessor, released in the 1980s, could accelerate floating-point calculations on IBM PCs by up to 100 times using complex algorithms implemented in microcode. The chip contains a microcod…
At the Supercomputing 2025 conference, Cornelis Networks CEO Lisa Spelman discussed the company's OmniPath architecture, a high-performance networking solution for HPC and AI workloads that was originally developed at In…
Nvidia's Blackwell B200 GPU is the company's first chiplet design, using two reticle-sized dies that appear as a single GPU to software, moving away from the monolithic approach used in prior generations like Hopper. The…
The z8086 is a compact, FPGA-friendly 8086/8088 processor core that runs original Intel microcode by loading a recovered 512x21 ROM, rather than hand-coding individual instructions. Written in about 2,000 lines of System…
At Supercomputing 2025, EuroHPC, AMD, and Eviden announced the Alice Recoque supercomputer, which will use AMD's upcoming Instinct MI430X GPUs to achieve over 1 Exaflop/s of sustained HPL performance while consuming less…
The Intel 8087, introduced in 1980, was a floating-point coprocessor that performed calculations up to 100 times faster than early microprocessors, significantly benefiting IBM PC applications like AutoCAD and spreadshee…
The article announces the release of an interactive online browser for the 8086 microprocessor's microcode ROM, created by the author after studying the original chip's design. The tool decodes every 21-bit micro-instruc…
This article evaluates the performance impact of NPS0 (Uniform Memory Access) mode on a dual-socket AMD EPYC 9575F system, provided by Verda (formerly DataCrunch). The analysis reveals that while NPS0 simplifies programm…
This article is a beginner-friendly guide to diagnosing and fixing AMD GPU issues on Linux, particularly for RDNA3 (RX 7000 series) cards. It explains common symptoms like system freezes and "fence timeout" errors, ident…
The Intel 386 processor, introduced in 1985 with 285,000 transistors, used standard cell logic—an automated place-and-route technique—to meet its production schedule after falling behind. The article examines unusual cir…
A team at the Department of Energy’s Oak Ridge National Laboratory used the Frontier supercomputer to run the largest-ever simulation of the observable universe, tracking over 4 trillion particles across 15 billion light…
Qualcomm's Snapdragon X2 Elite is a new system-on-chip for Windows on ARM, featuring 18 CPU cores (12 "Prime" and 6 "Performance") with Prime cores clocking up to 5.0 GHz. The Oryon Gen 3 cores include a wider 9-wide dec…
The **nvidia-smi** (NVIDIA System Management Interface) is a command-line tool for monitoring, managing, and diagnosing NVIDIA GPU devices, providing data on performance, temperature, utilization, power, and memory. It s…
The article describes the author's personal, non-expert workflow for using Handbrake in 2025 to compress movies and TV shows. They start with the Matroska AV1 preset, then adjust the encoder preset to 3 for better qualit…
AMD's Strix Halo mobile processor uses a 32 MB Infinity Cache as a GPU last-level cache to balance high bandwidth demands with power efficiency, supported by a 2 MB L2 cache and 256 KB L1 per shader array. The Infinity C…
Leica has announced the Leica M EV1, the first M-system camera to replace its traditional optical rangefinder with a built-in electronic viewfinder. The new EVF addresses limitations of the current M digital lineup, such…
The article evaluates the Infinity Cache in AMD's Strix Halo mobile chip (Ryzen AI MAX series), which combines a 16-core Zen 5 CPU with a 20-WGP RDNA 3.5 GPU and 32 MB of memory-side cache. The author uses programmable p…
AMD's Strix Halo is a high-performance chiplet APU announced at CES 2025, designed for mobile devices with a TDP range of 55W to 120W. It features up to 16 Zen 5 CPU cores, a 40-core RDNA 3.5 iGPU, and a 256-bit LPDDR5X-…
The article provides instructions for flashing firmware on Marvell/Aquantia AQC113 network controllers using the `flashUpdate2.exe` tool on Windows, including steps to disable memory protection and allow unsigned drivers…