Zettascale (YC S24) Is Hiring Founding FPGA Engineers

Zettascale (YC S24), a San Francisco-based AI chip startup, is hiring founding FPGA engineers to build its next-generation XPU compute engines designed to support artificial general intelligence and artificial superintelligence. The company seeks engineers with expertise in digital design, RTL, synthesis, and AI accelerator architecture to join its founding team and shape the future of AI compute infrastructure. The role offers significant equity and the opportunity to make critical technical decisions as the company scales.

We're Building the Next Generation of Chips to Power AI. Join Us. At Zetta, we're building the next NVIDIA to accelerate AI discovery. Our XPU chips are state-of-the-art AI compute engines , versatile and efficient enough to support AGI , and eventually ASI , without requiring massive power infrastructure. The team consists of exceptional engineers obsessed with pushing the boundaries of what's possible in computing, and we're now seeking our next technical member You Are Ready to go all-in and do the work of your life Willing to be hardcore when pushing technical boundaries - A technical powerhouse who loves working across the hardware-software boundary - Deeply passionate and obsessed with computing and AI - Hungry to build something that actually matters Your Background important in bold - Background in Electrical Engineering, Computer Engineering, or equivalent field Strong digital design fundamentals VLSI, RTL, pipelining, clocking/reset strategy, latency/throughput tradeoffs, clean microarchitecture RTL quality discipline lint, CDC/RDC, X-prop awareness, assertions/SVA, code review hygiene Synthesis/constraints expertise SDC constraints, synthesis/PPA iteration, timing closure with physical design Proficiency with front-end toolchains VCS/Xcelium/Questa, Verilator, SpyGlass-style linting, DC/Genus-class synthesis Build/flow automation and tooling Python, Tcl, Nix Work across architecture, verification, and physical design to hit PPA targets area/power/perf Experience designing compute datapaths and memory subsystems for AI accelerators, GPUs, or high-performance CPUs bandwidth/latency-driven design Huge Plus If High-speed interface/IP integration experience PCIe, CXL, DDR/HBM, Ethernet, SerDes DFT-aware RTL scan-friendly coding patterns, test hooks, clean resets, well-defined clock gating strategy Experience writing/maintaining reusable IP parameterization, clean bus protocols, well-structured interfaces 1+ years or equivalent designing synthesizable RTL SystemVerilog/Verilog for ASICs and/or high-performance FPGA prototypes HW/SW boundary experience drivers/firmware bring-up, performance counters, profiling, build systems Experience with systems programming Linux kernel modules, low-level - Autodidactic polymath with a strong mathematical background Someone who doesn't fret when faced with near-impossible technical challenges The Opportunity Be one of the first employees shaping a revolutionary technology - Work directly with the founding team of exceptional engineers at our San Francisco HQ - Own critical decisions that will influence the future of AI compute - Grow into a technical leader as we scale - Highly competitive compensation + significant equity This is THE chance to do the work of your life. The chance to build something that will be remembered. To go hardcore on a technical moonshot that will actually matter for over 100 to 1,000 years.