Xcena Cuts Data Movement to Address Memory Bottlenecks

South Korean startup Xcena detailed its MX1 CXL Type 3 device at Hot Chips 2026, combining up to 2 TB of DDR5, SSD-backed InfiniteMemory capacity, and more than 1,000 custom RISC-V cores. Xcena chief product officer Harry Kim said the MX1 delivers up to 4.7× the throughput and 18.7× the energy efficiency of a host CPU processing data over CXL on selected data analytics workloads. Xcena is sampling the MX1 prototype to memory vendors, CPU vendors, and hyperscalers, with mass production planned by the end of 2026 and initial customer revenue targeted for 2027.

Processing data closer to memory is not a new idea, but South Korean startup Xcena believes it has a better way to do it by leveraging the Compute Express Link CXL protocol. At Hot Chips 2026, the company detailed its MX1, a CXL Type 3 device that combines up to 2 TB of DDR5, SSD-backed InfiniteMemory capacity, and more than 1,000 custom RISC-V cores. Chief product officer Harry Kim said Xcena’s MX1 can deliver up to 4.7× the throughput and 18.7× the energy efficiency of a host CPU processing data over CXL on selected data analytics workloads. In a briefing with EE Times, Kim said the memory bottleneck can’t be solved simply by adding more memory; existing memory resources must be used more efficiently. “If we can reduce the data movement, then it will be really helpful,” he said. MX1 is particularly well suited to memory-intensive AI and database workloads where only a subset of stored data ultimately needs to be processed by CPUs or GPUs, Kim said. View All https://www.eetimes.com/category/sponsored-content/ For applications such as vector search, KV-cache operations, and database filtering, computation performed close to memory can reduce latency, power consumption, and bandwidth bottlenecks, he said. “For the database example, we can reduce data movement by filtering out the old data you don’t need to see from the CPU side.” For AI, it means pulling just the relevant slice of a KV cache, Kim said. Bringing together DDR5, SSDs, and RISC-V cores required solving significant software and memory management challenges because Xcena wanted to make the MX1 easy for customers to program, Kim said. “We want to keep the memory model as similar as what they want to do in the CPU side.” He said one of the biggest technical hurdles was creating a unified virtual memory system capable of maintaining mappings between host memory, device memory, and SSD-backed capacity. Xcena wanted MX1 to be, above all, a robust memory expander. Kim said it differentiates itself from competing CXL memory expansion products because it combines a full-featured memory controller with specialized near-memory processing capabilities. He said other computational CXL devices use general-purpose processors, while MX1 targets parallel data processing that uses all the internal bandwidth. The device’s computational capabilities rely on a many-core RISC-V architecture, which Kim said was influenced by the maturity of the RISC-V ecosystem. The company modified an LLVM-based compiler to support custom instructions and offers a CUDA-like SDK, so developers can write in C, C++, or Rust. Since managing thousands of processor cores remains challenging, Xcena developed a framework inspired by distributed database systems to simplify programming and workload management. Xcena is sampling the MX1 prototype to memory vendors, CPU vendors, and hyperscalers, and the company plans mass production by the end of 2026, with initial customer revenue targeted for 2027. Kim said a key dependency is broader industry adoption of CXL 3 running over PCIe 6.0, and while CXL adoption has been arguably slower than expected despite the rapid evolution of the protocol https://www.eetimes.com/cxl-adds-port-bundling-to-quench-ai-thirst/ , he doesn’t think the technology itself is at fault, noting that all the CPU and GPU vendors, including Nvidia, have built CXL into their chips. CXL is ready, Kim said, but its value still needs to be proven. Successful adoption requires a broader ecosystem, he said. “We need to prove CXL is good for everyone for AI infrastructure with CXL 3.” In a briefing with EE Times, Jim Handy, principal analyst with Objective Analysis, said Xcena’s MX1 architecture is an interesting combination, similar to the approach taken by computational storage. “It’s an interesting product,” he said. A recent Objective Analysis report https://objective-analysis.com/reports/ CXL , titled CXL Market Now Taking Shape, outlines how CXL is gaining adoption in the hyperscale computing community and how the technology now seems poised for significant growth. Handy said one of the most appealing capabilities of CXL today is memory expansion, but repurposing older memory, such as DDR4, instead of buying DDR5 at current prices, has also become a common use case. He noted that Facebook parent company Meta is using CXL-based memory expansion https://www.eetimes.com/meta-cuts-server-count-25-by-reusing-old-memory-can-anyone-else-do-it/ across millions of servers, reusing DDR4 modules pulled from decommissioned machines rather than retiring them. Handy said the memory pooling capability of CXL has yet to be widely used even though it’s a great idea. “There’s probably fire under the feet of the people who are developing pooling,” he said. “It improves the percent utilization that you get out of the memory chips you’ve already got, and if memory is really expensive, then you want to make sure that you’re not having any of it sitting around idle.” Also read: The Memory Super-Cycle: How Allocation Is Creating New Infrastructure Bottlenecks https://www.eetimes.com/the-memory-supercycle-how-allocation-is-creating-new-infrastructure-bottlenecks/ Identifying AI Bottlenecks: Memory, Scale, and Sparsity https://www.eetimes.com/podcasts/fixing-ais-bottlenecks-memory-scale-and-sparsity/ Renesas Tackles Memory Bottleneck with MRDIMM Update https://www.eetimes.com/renesas-tackles-memory-bottleneck-with-mrdimm-update/