x86S w/ IGZO BEOL eDRAM

A developer explored combining Intel's x86S architecture with IGZO-based eDRAM technology, using a Gemini prompt to analyze the implications. The work references imec's capacitor-less IGZO DRAM research and Intel's 5-level paging, suggesting a potential shift to 64-bit-only boot processes.

Building on recent X86 news, I ran this through a Gemini Prompt https://share.gemini.google/Eh58bqsyB5pI : https://github.com/hatonthecat/solarcircuits/commit/ebbc2dfca3f293927b0a75a191695b03db609227 https://github.com/hatonthecat/solarcircuits/commit/ebbc2dfca3f293927b0a75a191695b03db609227 https://www.imec-int.com/en/articles/disrupting-dram-roadmap-capacitor-less-igzo-dram-technology https://www.imec-int.com/en/articles/disrupting-dram-roadmap-capacitor-less-igzo-dram-technology https://en.wikipedia.org/wiki/Intel 5-level paging https://en.wikipedia.org/wiki/Intel 5-level paging https://www.phoronix.com/news/x86-CPU-With-APX-x86S https://www.phoronix.com/news/x86-CPU-With-APX-x86S https://en.kocpc.com.tw/archives/25278 https://en.kocpc.com.tw/archives/25278 "PM64-only means the core boots straight into 64-bit protected mode"