{"slug": "x86s-w-igzo-beol-edram", "title": "x86S w/ IGZO BEOL eDRAM", "summary": "A developer explored combining Intel's x86S architecture with IGZO-based eDRAM technology, using a Gemini prompt to analyze the implications. The work references imec's capacitor-less IGZO DRAM research and Intel's 5-level paging, suggesting a potential shift to 64-bit-only boot processes.", "body_md": "Building on recent X86 news, I ran this through a [Gemini Prompt](https://share.gemini.google/Eh58bqsyB5pI):\n\n[https://github.com/hatonthecat/solarcircuits/commit/ebbc2dfca3f293927b0a75a191695b03db609227](https://github.com/hatonthecat/solarcircuits/commit/ebbc2dfca3f293927b0a75a191695b03db609227)\n\n[https://www.imec-int.com/en/articles/disrupting-dram-roadmap-capacitor-less-igzo-dram-technology](https://www.imec-int.com/en/articles/disrupting-dram-roadmap-capacitor-less-igzo-dram-technology)\n\n[https://en.wikipedia.org/wiki/Intel_5-level_paging](https://en.wikipedia.org/wiki/Intel_5-level_paging)\n\n[https://www.phoronix.com/news/x86-CPU-With-APX-x86S](https://www.phoronix.com/news/x86-CPU-With-APX-x86S) \n\n[https://en.kocpc.com.tw/archives/25278](https://en.kocpc.com.tw/archives/25278) \"PM64-only means the core boots straight into 64-bit protected mode\"", "url": "https://wpnews.pro/news/x86s-w-igzo-beol-edram", "canonical_source": "https://inavoyage.blogspot.com/2026/09/x86s-w-igzo-beol-edram.html", "published_at": "2026-09-09 15:10:55+00:00", "updated_at": "2026-09-09 15:23:55.525010+00:00", "lang": "en", "topics": ["artificial-intelligence"], "entities": ["Intel", "imec", "Gemini"], "alternates": {"html": "https://wpnews.pro/news/x86s-w-igzo-beol-edram", "markdown": "https://wpnews.pro/news/x86s-w-igzo-beol-edram.md", "text": "https://wpnews.pro/news/x86s-w-igzo-beol-edram.txt", "jsonld": "https://wpnews.pro/news/x86s-w-igzo-beol-edram.jsonld"}}