# Unifying Edge AI: How Coral NPU’s open standard brings portable, energy-viable intelligence from model to silicon > Source: > Published: 2026-10-20 13:18:28.195453+00:00 Some of the most compelling use cases for AI are happening directly on the devices around us. You see it first in personal devices like wearables that need to understand context in real time, and increasingly in enterprise and industrial systems like autonomous robots and smart sensors. These experiences require low latency, strict privacy, and all-day reliability that cannot depend on a constant round-trip to the cloud. Edge AI complements the cloud to bring the best AI experiences. These rely on a continuous flow of context and intelligence across both, working as a model cascade where information is captured and processed in the right place at the right time. Ultra-low-power models on the edge can continuously sense and respond in real time, while seamlessly handing off to larger on-device or cloud models when deeper reasoning is needed. Still, building for the edge is much harder than it should be. While cloud infrastructure has converged around a few standard software stacks, the edge is split across hundreds of proprietary chip architectures and incompatible toolchains. For ML developers, this creates a heavy fragmentation tax, where you end up rewriting kernels, re-quantizing models, and debugging vendor-specific compilers for every chip you target. Last year, Google Research [introduced Coral NPU](https://developers.googleblog.com/introducing-coral-npu-a-full-stack-platform-for-edge-ai/) with a simple idea: an open hardware and software standard is the only way to unify the edge and unlock developer productivity and portability. Our standards based, ML-first RISC-V architecture paired with a reliable open-source toolchain gives developers confidence that their models will compile and run, letting teams optimize a model once and deploy it across different SoC vendors, devices, and power envelopes. Today, we are reaching three major milestones in the Coral effort: Fixing fragmentation at the edge takes more than publishing an instruction set. Historically, many edge accelerators were designed to hit high peak-compute numbers on spec sheets, leaving compiler teams to figure out software support later. In practice, unsupported neural network layers fall back to a general-purpose CPU, which can hurt latency and drain the battery. We designed the Coral NPU architecture and its compiler together from the start. Instead of chasing peak metrics, our focus is on energy-viable compute: helping to deliver the right performance at the right power envelope for your application. Over the past year, [we released the first three milestones](https://developers.google.com/coral/guides/roadmap) of the 32-bit Coral NPU design: a C-programmable RISC-V scalar frontend for control flow (Milestone 1), an RVV v1.0 vector co-processor for SIMD operations (Milestone 2), and a tightly coupled memory subsystem with floating point support (Milestone 3). With this month's release of the Matrix Execution Unit (Milestone 4), the 32-bit architecture is complete. Scalar and vector units are great for general control logic and signal processing, but modern ML workloads—from vision encoders to transformer attention layers—spend most of their time on 2D matrix-matrix (GEMM) and matrix-vector (GEMV) multiplication. Running 2D matrix math on a 1D vector engine forces the chip to repeatedly load weights and activations from memory, which can mean spending more energy moving data than doing math. Our Matrix Execution Unit leverages the RISC-V VME specification (formally part of the Zvt family) to address this need and uses a dedicated outer-product multiply-accumulate (MAC) engine. Because an outer-product engine computes a full 2D tile of operations in a single cycle (256 MACs per cycle), it reuses weights and activations directly inside local registers. This brings quadratic throughput scaling to the core, configurable for up to 1 TOPS. Having a dedicated matrix engine in a sub-10 mW envelope changes what developers can build on a small battery. Rather than stopping at simple keyword spotting or basic motion detection, devices can run continuous, multimodal workloads, including compact transformer models like Gemma, real-time voice translation on wearables, spatial audio filtering on hearables, and low-latency visual perception on robots. To help silicon teams bring this open design straight into commercial production, the complete [32-bit RTL](https://github.com/google-coral/coralnpu) is available today on GitHub. To make the hardware easy to target without writing custom assembly, we are also releasing the v1.0 foundation of our [open-source MLIR/IREE compiler toolchain](https://github.com/google-coral/coralnpu-compiler). With this stack, you can bring models from JAX, PyTorch, or TensorFlow through standard representations like StableHLO and TOSA. The compiler partitions workloads between the host CPU and the Coral NPU core, handles operator fusion, tiles matrices to fit local SRAM and matrix accumulators, and progressively lowers workloads directly to Coral NPU scalar, RVV v1.0 vector, and VME matrix instructions. Alongside our open-source MPACT simulator and reference FPGA design, hardware and software teams can benchmark models and tune silicon configurations before a chip ever goes to fabrication. Turning an open standard into commercial silicon takes collaboration across the entire semiconductor value chain. To help silicon partners bring this open design straight into commercial production, the complete 32-bit RTL is available today on GitHub, and we are partnering with [VeriSilicon](https://www.verisilicon.com/) on the design implementation and verification (DV) to ensure turnkey readiness for silicon tape-outs. We are also working with [GlobalFoundries](https://gf.com/) on their 12LP+ FinFET process - accelerating core timing by 70%, and reducing standard-cell area by up to 15% across RTL iterations, with ongoing evaluation of 12LP+ ultra low-power libraries for the Matrix Execution Unit. On the commercial silicon side, our collaboration with Synaptics shows how quickly this open standard translates into real hardware across very different power budgets without splitting the software experience. At Synaptics Tech Day (October 20, 2026), Synaptics is launching three [commercial silicon](https://www.synaptics.com/sr200-press-release) and [hardware products](https://www.synaptics.com/coralboard-press-release) built on Coral NPU technology and supported by the open IREE/MLIR toolchain: Because both product families build on the same architecture and compiler foundation, ML teams can optimize a model once and deploy it to a milliwatt-class wearable (Coralboard SR) or a 1 TOPS board (Coralboard SL) using the same workflow. Developed in collaboration with hardware and System-on-Module partner [Grinn](https://grinn-global.com/), the Coralboard lineup also gives teams a direct path from devkit prototyping to commercial production hardware. With our 32-bit architecture and v1.0 compiler stack in place, we are already working on the next phase of the roadmap, including a 64-bit Coral NPU architecture and CHERI support for security. Whether you are designing a custom edge SoC, working on ML compilers, or deploying models to wearables and robotics, Coral NPU can help give you an open path from model to silicon. Here is where you can get started: