UART in Verilog with Fractional Clock Dividers

The article discusses a challenge with implementing UART communication in FPGAs when the system clock frequencies are not integer multiples of the desired baud rate, leading to imprecise timing and errors. The author presents a solution using fractional clock dividers to achieve accurate baud rates, specifically for a 1Mbps UART connection between FPGA cores and an MCU. This technique addresses the limitations of traditional integer dividers in mixed-frequency embedded systems.

Universal Asynchronous Receiver-Transmitter UART modules are basic components in embedded systems, enabling serial communication between devices. While there are many free implementations available online, a new challenge arose during my work on the independent software stack for the Tang Console: non-integer clock multiples. This issue surfaced when FPGA cores running on clocks of different frequencies need to communicate with an MCU via UART. Unlike SPI, where the master dictates the clock, UART demands both sides to adhere to a pre-agreed-upon baud rate 1Mbps in my case . Traditional integer clock dividers in this case yield imprecise baud rates and communication errors. In this post, I’ll explore a nice solution using a fractional clock divider technique.