UALink – Ultra Accelerator Link – Open-Source/Hardware Alternative to NVLink

The UALink Consortium published version 2.0 of the Ultra Accelerator Link (UALink) open specification in April 2026, following the public release of the 1.0 (UALink_200) specification in 2025. UALink is a die-to-die interconnect and serial bus for AI accelerators co-developed by Alibaba, AMD, Apple, Astera Labs, AWS, Cisco, Google, Hewlett Packard Enterprise, Intel, Meta, Microsoft and Synopsys, positioning it as an open alternative to Nvidia's NVLink. The 1.0 specification runs at 200Gbps over the IEEE P802.3dj PHY layer, and UALink Switches (ULS) connect up to 1024 accelerators within an AI pod, each assigned a unique 10-bit routing identifier.

UALink | UALink | | |---|---| | Ultra Accelerator Link | | | Year started | 2024 | | First published | 23 October 2024 | | Latest version | 2.0 7 April 2026 | | Organization | UALink Consortium | | Related standards | Infinity Fabric https://en.wikipedia.org/wiki/Infinity Fabric , Ultra Ethernet https://en.wikipedia.org/wiki/Ultra Ethernet?action=edit&redlink=1 | | Website | ualinkconsortium http://ualinkconsortium.org | Ultra Accelerator Link UALink is an open specification https://en.wikipedia.org/wiki/Open specification for a die <https://en.wikipedia.org/wiki/Die integrated circuit -to-die interconnect <https://en.wikipedia.org/wiki/Interconnect integrated circuits and serial bus <https://en.wikipedia.org/wiki/Bus computing between AI accelerators https://en.wikipedia.org/wiki/AI accelerator . It is co-developed by Alibaba https://en.wikipedia.org/wiki/Alibaba Group , AMD https://en.wikipedia.org/wiki/AMD , Apple https://en.wikipedia.org/wiki/Apple Inc. , Astera Labs https://en.wikipedia.org/wiki/Astera Labs , AWS https://en.wikipedia.org/wiki/AWS , Cisco https://en.wikipedia.org/wiki/Cisco , Google https://en.wikipedia.org/wiki/Google , Hewlett Packard Enterprise https://en.wikipedia.org/wiki/Hewlett Packard Enterprise , Intel https://en.wikipedia.org/wiki/Intel , Meta https://en.wikipedia.org/wiki/Meta Platforms , Microsoft https://en.wikipedia.org/wiki/Microsoft and Synopsys https://en.wikipedia.org/wiki/Synopsys .<sup \ 1\ cite note-1 </sup The UALink Consortium officially incorporated as an organization and electronics industry https://en.wikipedia.org/wiki/Electronics industry consortium https://en.wikipedia.org/wiki/Consortium in 2024, for promoting and advancing UALink. Its first specification will provide interconnectivity specifically for a scalable network. The initial 1.0 version 200Gbps UALink specification, is based on the IEEE P802.3dj https://en.wikipedia.org/wiki/IEEE 802.3 200 Gb/s Ultra Ethernet PHY Layer. Each system node is made up of a host and as many accelerators as needed, and is managed by one OS image. The accelerators can be connected to the host using a variety of interconnect protocols CXL https://en.wikipedia.org/wiki/Compute Express Link , PCIe https://en.wikipedia.org/wiki/PCIe , XGMI, CHI c2c, Infinity Fabric https://en.wikipedia.org/wiki/Infinity Fabric . UALink Switches ULS connect up to 1024 accelerators within an AI 'pod', where each Accelerator is assigned a unique 10-bit routing identifier. Each UALink Switch port connects to a distinct Accelerator.<sup \ 2\ cite note-2 </sup AMD Infinity Fabric https://en.wikipedia.org/wiki/HyperTransport Infinity Fabric is expected to be the main shared-memory protocol. \ 3\ cite note-3 The specification was due to be available to Contributor Members in 2024.<sup \ 4\ cite note-4 </sup The 1.0 version UALink 200 was released to the public in 2025. Members of the public can download an "evaluation copy" after providing contact information. \ 5\ cite note-UA200 10EC-5 Version 2.0 of the specification was published in April 2026. \ 6\ cite note-6 References edit https://en.wikipedia.org/w/index.php?title=UALink&action=edit§ion=1 1. ↑ cite ref-1 "UALink Members UCIe" https://www.ualinkconsortium.org/members . ualinkconsortium.org . Retrieved 2024-11-01. 2. ↑ cite ref-2 "UALink 1.0 White Paper v3" https://web.archive.org/web/20250809025256/https://ualinkconsortium.org/wp-content/uploads/2025/04/UALink-1.0-White Paper v3.pdf PDF . Archived from the original https://ualinkconsortium.org/wp-content/uploads/2025/04/UALink-1.0-White Paper v3.pdf PDF on 2025-08-09. 3. ↑ cite ref-3 Morgan, Timothy Prickett 30 May 2024 . "Key Hyperscalers And Chip Makers Gang Up On Nvidia's NVSwitch Interconnect" https://www.nextplatform.com/connect/2024/05/30/key-hyperscalers-and-chip-makers-gang-up-on-nvidias-nvswitch-interconnect/1650834 . The Next Platform. Retrieved 19 May 2026. 4. ↑ cite ref-4 "ABOUT UALINK" https://www.ualinkconsortium.org/about-ualink . UALink Consortium . Retrieved 2025-01-20. 5. ↑ cite ref-UA200 10EC 5-0 "Ultra Accelerator Link Consortium, Inc.™ UALink 200 Rev 1.0 Specification" https://ualinkconsortium.org/specification/ . ualinkconsortium.org . pdf https://ualinkconsortium.org/wp-content/uploads/2025/04/UALink200 Specification v1.0 Evaluation Copy.pdf 6. ↑ cite ref-6 Cooter, Maxwell 7 April 2026 . "New v2 UALink specification aims to catch up to NVLink" https://www.networkworld.com/article/4155357/new-v2-ualink-specification-aims-to-catch-up-to-nvlink.html . Network World. Retrieved 19 May 2026. See also edit https://en.wikipedia.org/w/index.php?title=UALink&action=edit§ion=2 External links edit https://en.wikipedia.org/w/index.php?title=UALink&action=edit§ion=3 - Ultra Ethernet Consortium https://ultraethernet.org has a draft-sharing relationship with IEEE P802.3dj