# TYL Semi De-Risks Chiplets With New Business Model > Source: > Published: 2026-07-15 19:00:00+00:00 With a fresh $43 million in seed funding, TYL Semi has developed a new type of fabless semiconductor business model: the startup wants to de-risk AI infrastructure builders’ big chiplet-based designs by handling everything around their compute chiplets, including surrounding chiplets, packaging, and test. Nobody owns such a chiplet platform today, TYL Semi cofounder and CEO Mohit Gupta told EE Times, since the custom silicon market is simultaneously polarized and fragmented. “Companies like Broadcom and Marvell have the ability to do the entire thing, but they position themselves as all or nothing engagements, and they are focused on opportunities that yield billions of dollars a year in revenue,” Gupta said. “On the other side you have a mix of IP and services companies […] where it’s fragmented and you have to work with a bunch of companies and you are carrying the risk, because nobody’s holding that risk for you.” Responding to geopolitical and supply chain factors, AI frontier labs and hyperscalers are going vertical, building silicon in-house for their own needs. [View All](https://www.eetimes.com/category/sponsored-content/) “They need better control, a better pricing mechanism and not to be locked into any vendor’s ecosystem,” he said. “[Generally] the pedigree of the team in AI companies isn’t semiconductors, because that’s not what they are selling in the market; they are selling services or models.” Companies like these need a partner to minimize the risk associated with developing large, multi-supplier chiplet designs and their supply chains. TYL Semi wants to take on that risk without becoming an ASSP company or a work-for-hire design services company. “We are positioning ourselves as a pure-play chiplet partner,” Gupta said. “If someone is trying to build their own silicon with a sophisticated silicon operations team that can handle known good die, we can provide [chiplets], or we can be your full custom silicon provider with the ability to provide the silicon end-to-end.” End-to-end means packaged, tested, and qualified silicon, Gupta said. TYL Semi is working with foundries, substrate, packaging, and test companies, noting that even for known-good die (KGD), different definitions of “known” and “good” exist across the industry. “The sophistication required to do [end-to-end chiplet-based chip design] is so high and there is a lack of people who have experience building these chips, and experience does matter on the custom silicon side,” he said. The timing is right for a new business model centered on chiplets, Gupta said. Not only are maturing standards and packaging driving the industry forward, but shifting geopolitical realities mean supply chains matter more than ever. “The benefits of chiplets are beyond the yield—the amount of compute and the complexity we are pushing in means chiplets are inevitable,” Gupta said. “Customers focus on how to build their [math engine] with the best performance and PPA, they don’t want to spend resources figuring out I/O or power delivery for that chiplet, those components can be purchased from outside.” TYL Semi will offer time-to-market advantage, reduced risk, and economic advantages, Gupta said, by working with customers in one of two ways. The first is for TYL Semi to build the entire chiplet-based design for the customer via its TYL.Forge platform. Customers can come with RTL or a netlist for their compute chiplets, and TYL Semi will tape out compute chiplets, add its own surrounding chiplets, have the silicon manufactured, packaged, tested, and delivered back to the customer. The second is for TYL Semi to sell its own TSMC-manufactured chiplets separately to customers who already have a sophisticated silicon design team in place. The first chiplets in TYL Semi’s portfolio are TYL.IO and TYL.Power. TYL.IO is a family of I/O chiplets supporting PCIe, ESUN and UALink, with PCIe Gen7 the first to tape out. TYL.Power is an integrated voltage regulator (IVR) chiplet. These two chiplets will be sampled in 2027. A memory connectivity chiplet, TYL.Mem, and a co-packaged optics chiplet are further down the roadmap. TYL.Forge, TYL Semi’s full-stack platform, which can combine custom compute and fabric chiplets with TYL’s connectivity and power delivery chiplets, is already engaged with lead customers, Gupta said. “We are a three-month old company and we are already engaged with a tier-1 semiconductor company who will buy some of our chiplets,” he said. “We are targeting another couple of design wins before the end of this year.” Gupta said he is being careful not to take on too much before the company can grow—TYL Semi’s headcount is currently 35 but will grow by around 80 this year across its U.S. HQ, Indian design center, and a new office due to open in Taiwan shortly. “We are engaging with a lot of hyperscalers to get our product definitions right,” Gupta said. “We want to understand what they are going to build in ’29 and ’30 so the product definition for those chiplets is right.”