{"slug": "tsmc-highlights-cowos-strength-over-panel-packaging-for-largest-ai-chips", "title": "TSMC highlights CoWoS strength over panel packaging for largest AI chips", "summary": "At TSMC's European Technology Symposium, Kevin Zhang, TSMC's senior vice president, stated that wafer-level packaging technologies like CoWoS currently offer superior interconnection density for the largest AI chips compared to panel-level approaches such as CoPoS, due to geometric complexity in panel processes. The remarks highlight TSMC's emphasis on CoWoS for high-density AI processor packages, even as the industry explores panel-based scaling for larger multi-die designs.", "body_md": "# TSMC highlights CoWoS strength over panel packaging for largest AI chips\n\nAt TSMC's European Technology Symposium, Kevin Zhang, TSMC's senior vice president of business development and global sales and deputy co-COO, said that panel-level packaging technologies such as CoPoS will not initially match the interconnection density of wafer-level packaging methods like CoWoS, according to Tom's Hardware. The Tom's Hardware report describes ongoing development of very large packages, including wafer-level approaches that could scale to packages containing as many as **58** dies. Zhang warned of geometric complexity in panel processes, saying, \"The geometry complexity panel-based process has to deal with is nowhere near the wafer level technology capability.\" The article frames CoPoS as a route to drive interposer scaling but presents CoWoS as currently superior for the highest-density AI processor packages.\n\n### What happened\n\nAt TSMC's European Technology Symposium, Tom's Hardware reports that Kevin Zhang, TSMC's senior vice president of business development and global sales and deputy co-COO, contrasted panel-level packaging (referred to in coverage as CoPoS) with wafer-level packaging technologies such as CoWoS. The article quotes Zhang: \"The geometry complexity panel-based process has to deal with is nowhere near the wafer level technology capability.\" Tom's Hardware also describes development work toward very large packages, including wafer-level approaches that could scale to packages containing up to **58** dies in a single unit.\n\n### Technical details\n\nPer the Tom's Hardware writeup, the core technical distinction highlighted by Zhang is interconnection density. The coverage frames wafer-level technologies like **CoWoS** as offering higher routing density and finer interconnect geometries today, while panel-level approaches such as **CoPoS** can enable larger physical package areas but face greater geometric complexity when matching wafer-level interposer routing. The article attributes the panel-versus-wafer contrast and the quoted assessment of process geometry directly to Zhang's remarks at the symposium.\n\n### Editorial analysis\n\nIndustry observers note that packaging choices trade off package size, interposer routing density, yield, and cost. Companies pursuing ultra-large AI processor packages often explore multiple routes in parallel: large-panel substrates for expanded area, and wafer-level interposers for dense die-to-die signaling. The balance between those approaches typically depends on target die count, latency and power budgets across interconnects, and manufacturability constraints at scale.\n\n### Context and significance\n\nFor practitioners designing multi-die AI accelerators, the distinction matters because interconnect density affects achievable bandwidth, latency, power per bit, and floorplanning options. Reported progress toward packages with dozens of dies, including the **58**-die figure cited in Tom's Hardware, underscores why both packaging ecosystems are active areas of innovation for hyperscalers and OEMs seeking larger effective processor sizes.\n\n### What to watch\n\nObservers should follow public technical disclosures and roadmap signals from foundries and OSATs on achievable interposer pitch, measured inter-die latency and power, and demonstrator packages. Separately, watch for additional symposium remarks or white papers from TSMC and OSAT partners that provide quantitative comparisons of routing density, yield, and thermal outcomes for CoWoS versus panel-based solutions.\n\n## Scoring Rationale\n\nThis is a notable infrastructure development: packaging choices materially affect multi-die AI processor bandwidth and design. The report is company-level technical commentary rather than a disruptive product release, so its practitioner impact is moderate but relevant to hardware and systems teams.\n\nPractice interview problems based on real data\n\n1,500+ SQL & Python problems across 15 industry datasets — the exact type of data you work with.\n\n[Try 250 free problems](/problems)", "url": "https://wpnews.pro/news/tsmc-highlights-cowos-strength-over-panel-packaging-for-largest-ai-chips", "canonical_source": "https://letsdatascience.com/news/tsmc-highlights-cowos-strength-over-panel-packaging-for-larg-8f7926dd", "published_at": "2026-06-16 11:20:24.148019+00:00", "updated_at": "2026-06-16 11:20:26.985040+00:00", "lang": "en", "topics": ["ai-chips", "ai-infrastructure"], "entities": ["TSMC", "Kevin Zhang", "CoWoS", "CoPoS", "Tom's Hardware"], "alternates": {"html": "https://wpnews.pro/news/tsmc-highlights-cowos-strength-over-panel-packaging-for-largest-ai-chips", "markdown": "https://wpnews.pro/news/tsmc-highlights-cowos-strength-over-panel-packaging-for-largest-ai-chips.md", "text": "https://wpnews.pro/news/tsmc-highlights-cowos-strength-over-panel-packaging-for-largest-ai-chips.txt", "jsonld": "https://wpnews.pro/news/tsmc-highlights-cowos-strength-over-panel-packaging-for-largest-ai-chips.jsonld"}}