AIArticle An engineer in Trinidad just gave the sharpest RISC-V critique in years its best answer.
Rachel Goldstein The best RISC-V argument of the year just played out between two embedded engineers who agree on almost every technical fact and disagree about what any of it means. Dmitry Grinberg — the hacker who once booted Linux on an 8-bit AVR — published "RISC-V: They Should Have Known Better," a long, sharp teardown of the ISA that hit the Hacker News front page. Days later, Armstrong Subero, an embedded engineer and Apress author who builds a RISC-V education platform from Trinidad and Tobago, answered with a rebuttal that also went to the front page. Read together, they're more useful than either alone, because they expose what the RISC-V debate is actually about: not encodings, but who gets to participate.
The critique is mostly right, and mostly beside the point #
Grinberg's technical complaints hold up. The compressed-instruction encodings really are strange — 16-bit byte stores get offsets of 0–3 where a Cortex-M0 gets 0–31. Immediates are scattered across instruction words in an order that makes emulator authors weep. Interrupt entry and exit on a base RV32 core costs roughly 44 cycles of register-stashing that a Cortex-M0 does in 27, in hardware. And the extension model means "RISC-V compliant" tells you nearly nothing: multiply, divide, CSRs, compressed instructions, privilege modes — all optional, with the misa
feature register itself optional and readable only from machine mode. Anyone who's shipped RISC-V firmware has hit some version of these. Subero, notably, concedes almost all of it.
But there's a structural oddity in the critique that the rebuttal nails. Grinberg derives, from first principles, what a cheap deeply-embedded core needs — small area, dense code, low interrupt latency, no divider, no privilege separation — and observes that he's just described RV32EC. He states flatly that RISC-V will own the cheap-microcontroller space, "not due to its ISA design, but despite it." Subero's response boils down to: you derived the requirements, the ten-cent chip on my desk meets them, and you're annoyed about the aesthetics. That's a fair hit. Whether an outcome was earned is an interesting question for ISA historians. It changes nothing for anyone deciding what to build on, because the parts exist either way.
The boundary is a contract, not an architecture #
The rebuttal's strongest move is reframing Grinberg's central claim — that high-end CPUs and cheap MCU cores have "diametrically opposed" requirements no single ISA can serve. In the ARM world, that boundary is real, but it isn't purely physics. It's product segmentation. Cortex-M has no MMU and never will; if you want virtual memory you license Cortex-A, a different profile with a different exception model, a different negotiation, and a different royalty. ARMv6-M, ARMv7-M, and ARMv8-A are genuinely different systems to learn.
On RISC-V, supervisor mode and paging are checkboxes in the privileged spec. The proof case is Baochip: someone bolted an MMU onto the open VexRiscv core, bunnie Huang built a 22nm SoC around it, and it now runs Xous, a Rust microkernel with real process isolation — with seL4 and Linux ports in progress. That chip shipped in this month's DEF CON 34 badge, and its dev board crowdfunded at $9.50. Nobody licensed anything. That's not an argument about encoding elegance; it's an argument that RISC-V moved the small-core/big-core boundary from a legal artifact to an engineering decision. Grinberg lists privilege separation among things the cheap end "does not need and therefore does not get" — Subero's point is that on ARM that's vendor policy wearing an architecture costume.
The same logic answers the fragmentation complaint, at least partially. The reason one base ISA can sit in a ten-cent part with sixteen registers and also under a protected multi-process OS is precisely that the small part isn't carrying the big part's baggage. Fragmentation and scalability are the same mechanism viewed from different ends. That doesn't excuse the sloppy parts — Zicsr not being implied by the base is a footgun, and vendor interrupt controllers are genuinely painful (Subero's own port of Apache NuttX to the CH32V307 meant wrestling WCH's proprietary PFIC instead of the standard CLIC). But it explains why the committee took the trade.
What this means if you're picking silicon #
The practical claim worth testing is Subero's vertical-stack argument, and it survives scrutiny. WCH's CH32V003 — RV32EC, 2KB SRAM, 16KB flash, machine mode only — really does sell for around ten cents, and fifty of them plus the WCH-Link debugger costs less than lunch. The CH32H417 puts a 400 MHz core, 896KB of SRAM, and an integrated 5 Gbps USB 3.2 Gen 1 PHY — something no mainstream Cortex-M offers; ST's dual-core H747 tops out at high-speed USB 2.0 — on a $20 evaluation board using that same cheap debugger. Above that sit Linux-class boards like the Orange Pi RV2, which launched around $30. Same base ISA, same register model, same calling convention, same GCC/Clang target from the disposable part to the desktop-shaped one. On ARM, that journey crosses three architecture profiles and, historically, a J-Link that costs more than all of the above combined.
Where you should stay skeptical: the portability claim covers the core, not the chip. Interrupt controllers, clock trees, and peripherals remain vendor-specific on RISC-V exactly as they are on ARM, and the extension soup means you must read the fine print — an RV32EC binary and an RVA23 profile part share a spiritual ancestor, not a software ecosystem. RISC-V International's profiles are the intended fix, and Grinberg is right that approximately no shipping application-class boards are fully RVA23-compliant yet. If you're betting a Linux product on RISC-V today, that limbo is your real risk, and it's a bigger one than any encoding quirk.
There's one more argument in the rebuttal that the spec-focused crowd shouldn't scroll past. Subero pays $60–$200 to ship parts that Americans get free shipping on, and has had distributors decline his region outright. From Trinidad — or Lagos, or Dhaka — a ten-cent part with an open toolchain, purchasable without export-verification friction, is the difference between thirty students each holding a chip and thirty students watching a demo. ISA elegance is a luxury of people whose hardware arrives.
So: Grinberg wins the argument about the spec, Subero wins the argument about the world, and the second argument is the one that moves silicon. The cheap end is already decided — RISC-V takes it, on price and availability, exactly as both authors predict. The contested ground is the middle and top, where fragmentation still bites and profiles haven't hardened. Elegance was never going to decide this. Access will.
Sources & further reading #
[A Third World Embedded Engineer Responds to "RISC-V: They Should Have Known Better"](https://rvembedded.com/blog_post/12/)— rvembedded.com -
[RISC-V: They Should Have Known Better](https://dmitry.gr/?amp=&proj=12.+RV&r=06.+Thoughts)— dmitry.gr -
[RISC-V: They should have known better](https://news.ycombinator.com/item?id=49305492)— news.ycombinator.com -
WCH CH32H417 dual-core RISC-V MCU offers USB 3.0, 500MB/s UHSIF, and Fast Ethernet interfaces— cnx-software.com - The DEF CON 34 Badge Packs a Surprise: Andrew "bunnie" Huang's "Mostly-Open" Baochip-x1— hackster.io
Rachel Goldstein· Dev Tools Editor Rachel has been embedded in the developer tooling ecosystem for nearly eight years, covering everything from IDE wars and package-manager drama to the quiet rise of AI-assisted coding. She has a soft spot for open-source maintainers and an unhealthy number of terminal emulators installed on a single laptop.
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