The Rackscale AI System Roadmaps That AMD Is Using To Chase Money

AMD is leveraging its rackscale AI system roadmaps to compete for datacenter spending, with CEO Lisa Su unveiling CPU and GPU plans at the Advancing AI 2026 event. The company has regained credibility after a decade-long recovery, now holding a 46% revenue share of the X86 server market, and is positioning its forthcoming 'Venice' Zen 6 CPUs, built on TSMC's 2nm N2 process, to deliver a 1.8X performance increase per socket over the current 'Turin' Epyc 9005 series.

The Rackscale AI System Roadmaps That AMD Is Using To Chase Money There is a saying that has been around for the past couple of decades in the datacenter, particularly with large enterprises and then solidified by the hyperscalers and the cloud builders: Customers don’t buy products, they buy roadmaps. The trick is, they also have to buy the roadmaps, with the sense of the word “buy” meaning “believe in” not literally meaning the acquisition of products. Chip maker AMD lost a whole lot of credibility when it walked away from the datacenter a decade and a half ago, which was before Lisa Su took the helm of the company and spun AMD’s ship right around and pointed it into the giant wave of datacenter spending and profits. The Great Recession and bugs with the Opteron server CPUs hit at the same time that Intel had finally gotten its act together with its “Nehalem” Xeons, and AMD needed to take a breather in the datacenter to focus on protecting its PC chip business. It has taken a decade for AMD to regain its credibility, and frankly, after watching Intel go up on the rocks and seeing its products and foundry hulls breached, AMD not only has roadmaps that are absolutely trustworthy in their own rights but looks good by comparison to Intel. AMD is without question competitive with AI industry juggernaut Nvidia on the hardware front, from chips to rackscale systems, and is getting it done on the software front with the help of hyperscalers and cloud builders who desperately want an alternative – or two, if you count their own XPU and CPU chippery – to the Nvidia stack to keep the heat on Big Green as well as to mitigate some pretty hefty supply chain risks here in the middle 2020s. So now, AMD roadmaps are a lot more fun, and Su was clearly having run unfolding its CPU and GPU roadmaps for the world to see at last week’s Advancing AI 2026 event in Silicon Valley. Let’s start with the server CPU roadmaps, with some drilldown on details with the forthcoming “Venice” Zen 6 CPUs. Su reminded everyone that AMD had about a 0.0 percent market share in server CPUs back in 2015 when it committed to get back into the game and when the first generation “Naples” Epyc CPUs launched two years later. And now, in early 2026, AMD has a 46 percent revenue share of the X86 server market. It will not be long before AMD is selling more server CPUs than rival Intel, which used to utterly own the X86 server CPU franchise excepting a few go-go years with Opterons back in the early 2000s. What Su did not point out, but which I will, is that Arm-based CPUs, driven mostly by the homegrown CPUs from the hyperscalers and cloud builders but also by the “Grace” CG100 CPUs from Nvidia that are embedded in all of its rackscale systems, now account for around half of server shipments and half of server revenues. We have not done the math yet on all of this, but the X86 pie slice is not growing as fast as the Arm pie slice is, and it is Intel, not AMD, that is bearing the brunt of the Arm assault. The “Turin” Epyc 9005 chips, which debuted in October 2024 https://www.nextplatform.com/compute/2024/10/10/amd-turns-the-screws-with-turin-server-cpus/1661158 , have 128 cores and 256 threads in the Zen 5 variant and have 192 cores and 384 threads in the Zen 5c variants that cut the L3 cache in half to cram on 50 percent more cores. The follow-on Venice Epyc 9006 lineup, coming with Zen 6 and Zen 6c core variations, will have a bunch of different variants, according to Su. The Epyc 9006s have compute cores etched using 2 nanometer N2 processes from Taiwan Semiconductor Manufacturing Co and using 6 nanometer processes on the I/O dies and memory controllers that the compute dies link into. The Venice cores will have higher frequencies and higher instructions processed per clock cycle IPC , and the Venice chips will have more cores, and together for the top end parts, that yields a 1.8X increase in performance per socket for like-for-like Turin to Venice comparisons. This is specifically referring to SPEC integer 2006 performance. The Venice CPUs will be the first server compute engines to sport PCI-Express 6.0 peripheral slots, by the way. The top end Venice Zen 6c version will sport 256 cores and 512 threads, which is 33 percent higher than the Turin Zen 5c. This Venice 6c socket will have eight compute complex dies with 32 cores each. This chip will also have 1.6 TB/sec of aggregate memory bandwidth on DDR5 DIMMs on the SP7 socket, which has 16 memory controllers that support 12.8 GHz MRDIMMs or 8 GHz RDIMMs. AMD is focusing on faster memory, not newer DDR6 memory that will have lower yields and higher costs initially. The idea is to give agentic AI sandboxes, which are performing tasks usually in Python rather than thinking, the highest performance per rack and per watt and per dollar, “bar none,” according to Su. The top end Venice Zen 6 part has 128 cores, half as many as the Zen 6c part, and is optimized for lower cost and is aimed at enterprise back office, analytics, and web infrastructure workloads. We strongly suspect that this part will plug into the smaller SP8 socket, which will have eight memory channels instead of the sixteen supported in the SP7 socket. There is another Epyc 9006 chip called the Venice HF, which has eight chiplets in the socket but they only have a dozen Zen 6 cores on each chiplet so the clock speed can be cranked up to 5 GHz for extremely high single-threaded performance on the cores. Hopefully this will be an SP7 socket with full memory capacity and bandwidth to keep those fast cores fed. . . . We think that HPC shops might love this chip as well, provided it has full 512-bit vector support. Which it will. There will be a Venice-X version with 3D vertical cache expansion for HPC and AI workloads that are cache sensitive. And a variant of Venice coming in 2027 called “Verano” will use LPDDR5 memory instead of regular DDR5 DIMMs, just like Nvidia’s Grace CPUs do and its future “Vera” CV100 server CPUs will do. The Verano chip is aimed at AI host nodes that do not need a huge processor and memory complex. Thios that do will use some variant of a dual-socket Venice 5 part. Here is how Su stacks up the Venice chips on the three core workloads – AI host servers, agentic AI sandboxes, and general purpose datacenter applications – against Intel’s various Xeon 6 chips and its own Turin Epyc 9005s: As we have pointed out before, in the current scarce market, if you can make a CPU, you can sell a CPU. And this is a damned convenient thing for Intel, which is going to be lagging AMD in performance and performance per watt for the foreseeable future. The question I have is would AMD sell more CPUs if it made more? Perhaps, but perhaps not given the way companies buy servers and have their own CPU prejudices and preferences. Here is how Su stacks up Venice and Turin against Nvidia’s forthcoming Vera server CPU and Arm’s name-limiting and also forthcoming AGI CPU: Those big gaps in performance tell you how much room AMD has to charge a premium for its Venice CPUs. If AMD only charges half as much as the average gap, it will still win in the price/performance analysis by a wide margin. We shall see when Venice launches, probably in the fall, this year. And here, Su picks on her cousin Jensen Huang’s Vera processor in particular on the SPEC integer 2006 benchmarks, pitting the 96 core Venice HF Zen 6 and 256-core Venice 256c Zen 6c parts against the 88 core Vera CPUs: As you can see, the Venice HF part has a 20 percent lead on raw integer performance, and the Venice 256 part has a 2.2X performance lead even though it has lower clock speeds and half the L3 cache per core. Having 2.67X the number of cores at 3.4 GHz would deliver that 2.2X performance beatdown over the Vera chip shown in the chart above. At this point, however, companies are thinking in terms of how many cores they can put into a CPU server rack for agentic sandboxes. Different Venice 256c server designs yield different results: There is only way to build a Vera MGX rack with Nvidia components, and that is with 22,528 cores per rack. AMD VENICE VERA RACKS COMPARE What this chart doesn’t show is relative performance per rack, so I included estimates of the performance of each Venice rack relative to the Vera MGX rack using the SPEC integer 2006 benchmark results shown further up in this story. The RPERF relative performance figure I made up is reckoned against the performance of a two-socket Vera-Vera server. That is all the new stuff about Venice, so let’s keep going and look at the Epyc roadmap: The Epyc CPU roadmap is staying on a two year cadence, which frankly is about all that the server industry can handle. It is reasonable to expect that AMD will try to intersect with the 1.4 nanometer A14 process node at TSMC as well as the competing 14A node at Intel so it might have two foundries to play against each other and to mitigate risks, which are political as well as technical and economical. China could invade Taiwan any damned day it feels like it. . . . And with TSMC and Intel both having advanced foundry capacity in the United States, the odds are higher that it will do just that. We know for sure that there will be Zen 7 and Zen 7c core variants, and is reasonable to assume that these Florence compute engines will shift to DDR6 main memory and keep PCI-Express 6.0 peripherals. We expect some advanced packaging as well, but it is hard to guess what might be coming. We do know there will be several variants of Florence, aimed at the three different workloads: AMD is giving the agentic AI sandbox variant its own codename as well as the AI host node. The Florence chips will plug onto the same SP7 and SP8 sockets where appropriate, and be mounted on cards like the Verano variant of Venice for AI host machines. We are curious to know what “Fidenza” will be and how it will differ from the approach taken with the Venice HF part it will replace in the Epyc lineup. It is debatable that any of the Venice or Florence variants merit a unique codename at all, excepting the fork between the Zen and Zen c cores. The software running on a Windows Server or Linux machine doesn’t even care about that distinction, really. The cores just have a different performance profile but not a different abstraction level for the software. Instinct GPU Compute Engines And Helios Rackscale Systems That is the update on the Epyc CPUs. So let’s dive into the Instinct MI400 series update that Su gave. We will start with the MI400 series and then take a look at the roadmap out to the MI500 and the MI600 GPUs and their related “Helios” rackscale system implementations. Right now, AMD is talking about two MI400 series GPUs: The MI455X, which is aimed at AI workloads, and the MI430, which is aimed at traditional HPC ModSim workloads. The MI455 has a dozen compute and I/O chiplets and is implemented in a mix of N2 and N3 processes from TSMC. The compute tiles are always on the smaller process because compute handles a process shrink a whole lot better than I/O and memory controllers do. SerDes SerDeses? are fussier than cores. The MI455X is rated at 20 petaflops at FP8 precision and 40 petaflops at FP4 precision, based on the CDNA 5 architecture, and has an astounding 432 GB of HBM4 capacity across a dozen controllers wrapped around the double-chiplet Altair compute complex. The Altair compute and I/O complex has 320 billion transistors. It looks like this: Those dozen HBM4 stacks provide a total of 23.3 TB/sec of aggregate memory. I will be drilling down into the MI455 architecture separately. But this MI455X thing is an absolute beast of a thing. The MI430X is rated at 288 teraflops at FP64 precision, and that will be 8.7X higher than the 33 teraflops that the “Rubin” GR200 GPU from Nvidia will have on its tensor cores. Nvidia is looking at Ozaki emulation of FP64 on lower precision hardware to give it higher FP64 throughput. It remains to be seen how the HPC community will feel about this. The MI430X will have the same 432 GB of HBM4 memory as the MI455X, which is great, and the same 23.3 TB/sec of bandwidth on that memory. That is 50 percent more capacity and 6 percent more bandwidth than the Vera GPU from Nvidia that comes later this year. The MI430X will ship in the first half of 2027, which gives Vera a slight jump. But only among those who can get Vera allocations from Nvidia, of course. The Helios rack will initially ship later this year with the 96 core Venice HF processor matched with four Altair MI455X GPUs linked by UALink over Ethernet with some as yet unknown Ethernet switch. We presume the CPUs and the GPUs are linked for coherent memory sharing over this same UALink protocol, but it may be Infinity Fabric linking the CPUs to the GPUs. The Pensando “Salina” DPU is used to virtualize storage and networking out to the front end network, and customers can choose a Broadcom “Thor Ultra” or Pensando “Vulcano” 800 Gb/sec AI NIC to scale out their Helios racks. There are 72 MI455X GPUs and 18 Venice HF CPUs in the double-wide Helios rack. Here is how Su stacked up the initial Helios rack against Cousin Jensen’s Vera-Rubin NVL72 rackscale system in terms of feeds and speeds: This was for dense matrix math operations. As you can see, AMD is edging out Nvidia on the raw feeds and speeds, with big jumps for HBM memory capacity and bandwidth. This should matter for actual workloads running. The Helios rack has 4,600 CPU cores and 18,000 GPU compute complexes. Sue gave some comparisons of how the Altair MI455X performed against the prior “Antares” MI355X GPU accelerator and made some vaguer claims about performance at the rack level compared to Vera-Rubin racks coming later this year. Here is the inference throughput using the DeepSeek V4 Flash model: As with other GPUs and XPUs, the increase in capacity across all fronts in the MI455X device yields higher token throughput, and particularly at the higher interactivity levels where users need more tokens processed. Here is how AMD reckons the cost per token on DeepSeek V4 Flash on the two different GPUs: As you push out to higher levels of interactivity, the MI455X makes much better sense than the MI355X it replaces in the Instinct lineup. Even at low interactivity levels, the MI455X looks to be half as expensive per token per second per user. Su said that the Helios rack with MI455X and Venice compute engines would yield about 15 percent better tokens per second per GPU on low interactivity inference, about 12 percent at medium interactivity, and about 10 percent on high interactivity. This was using the Kimi K2 Thinking model from Moonshot AI. She added that generally, the Helios rack would offer up to 30 percent more tokens per dollar than a Vera-Rubin NVL72 rack. Which brings us to the Instinct MI GPU roadmap, finally. Take a gander: The MI500 series will have a new architecture, CDNA 6, and not much is known about it. AMD has promised that MI500 will have 2,000X the performance of the MI300 series from four years ago, and that it will employ copper and optical interconnects, use HBM4E stacked memory, and have a “leadership GPU scale up domain.” That 2,000X performance metric is tokens per second per GPU , not per rack , for inference workloads, so this is not scale out or even scale up performance. I am curious to see how this is possible without 3D stacking of compute elements. I cannot believe we can do more than FP2 precision – FP0 anyone? – and even FP4, much less FP2, is dubious in terms of being useful for complex, high resolution data as far as I am concerned. The world is not text, and much as I love the written word. And if you are scanning high resolution medical images, I want FP64 precision as models look for bad stuff. In any event, MI600 is in development and will come to market in 2028. Finally, just like the Instinct GPUs have an annual cadence, the Helios racks also need a cadence to match those annually refreshed GPUs. And so that is what AMD is going to do: It is not at all clear what the differences will be across the Helios 400, 500, and 600 racks, but we know there is a transition to optical links alongside copper links with the Helios 500. The Helios 600 series could be all optical, which would be neat but perhaps risky for 2028. That feels like more of a 2030 move, when the industry has ramped production more for optical components.