{"slug": "system-design-for-physical-ai-a-chip-design-record-from-spec-to-tapeout", "title": "System design for physical AI: a chip design record from spec to tapeout", "summary": "Muhammad Umar published an open reference architecture, released under CC BY 4.0 with a JSON object model and model register, for a chip design record that traces specification changes through requirements, design blocks, verification checks, tests, coverage results, bugs and waivers at a fabless Saudi Arabian silicon company. The stack deliberately omits time-series stores, video ingest, edge serving and sensor synchronization, relying instead on Apache Kafka 4.3 in KRaft mode for ordering, Keycloak for identity, Harbor for artifact ingress and Prometheus, Grafana and Loki for monitoring, with GLM 5.3 served on vLLM at FP8 on a single node of eight 141 GB HBM cards. The design keeps vendor tools and the requirements site read-only behind a single integration adapter family, flags impact lists built from unreconciled revisions as stale, and permits writes only through an approval-gated path into version control.", "body_md": "*By Muhammad Umar. This is the engineering summary of an open reference architecture. The paper, its object model as JSON and the model register are free to reuse under CC BY 4.0: [https://codeatoms.ai/chip-design-ontology-saudi-arabia/](https://codeatoms.ai/chip-design-ontology-saudi-arabia/). DOI [10.5281/zenodo.23693146](https://doi.org/10.5281/zenodo.23693146). The operator is described by class, never by name.*\n\nA fabless chip design company in Saudi Arabia designs silicon in vendor design tool suites, verifies it through simulation and formal tools and hands tapeouts to an outside foundry. Its specifications run to hundreds of pages and keep changing. The verification lead's daily question is narrow: when an interface requirement changes on one block, which signals, checks, tests, coverage holes, open bugs and waivers does it touch, and which requirements have no proof at all. Five systems each hold one slice of that answer, and none of them joins the rest.\n\nThe shared specification drives, the requirements site, the version control system, the bug records and the vendor design tool suites are all read only. Every one enters through a single integration adapter family, which stamps each fact with the tool, file and revision it came from. The requirements site is projected, not replaced: the model holds requirements as objects with traceability links, and the company's own system stays authoritative. The vendor tools are integrated by exposure rather than connection, so the model sits beneath every vendor's tools instead of inside one vendor's silo. A reconciliation job runs after every sync cycle; an impact list built from an unreconciled revision is flagged stale and kept out of citations. The only write path is the approval-gated one into version control.\n\nThis is the unusual part for a physical AI design: there is no fab floor, no camera and no machine telemetry in scope. So the stack drops whole layers on purpose. No time series store, no video ingest, no edge serving, no edge orchestration, no sensor time synchronisation. Ordering comes from the event backbone's own sequencing and the version control system's commit order, because the only ordering that matters is which revision came before which approval. Apache Kafka 4.3 in KRaft mode, with three dedicated controllers and a dynamic quorum, holds a replicated, replayable log, so a service that falls behind replays instead of asking the sources again. Keycloak issues identities, Harbor's offline installer is the only inbound door for artifacts and models, and Prometheus, Grafana and Loki watch the system's own health.\n\nEverything runs in the company's own server room. GLM 5.3 is the agentic work surface, served on vLLM at FP8 from one node of eight 141 GB HBM cards. The arithmetic: 753 billion parameters at one byte each is 753 GB of weights, the 1.2 planning factor for KV cache and activations makes it 904 GB, and the node holds 1,128 GB, which leaves 375 GB beside the weights against the 151 GB the factor reserves. The node draws roughly ten kilowatts, and it is a 4A090 item for a D:4 destination, so a BIS licence determination is a phase one checkpoint; until the node lands, the platform runs on the company's existing hardware, and no smaller GPU class is silently substituted. BGE-M3 handles embedding and retrieval at FP16, about 1.1 GB, on CPU or a modest GPU. PaddleOCR-VL 1.6 parses specification tables, formulas and layout at ingestion, about 0.96B parameters at BF16, roughly 1.9 GB.\n\nThe object model holds the specification section, requirement, design block, interface, signal, design assumption, verification check, test, coverage result, bug, waiver, design revision, engineer, verification lead, expert lesson and foundry handoff. A query starts at a changed requirement, walks back to its specification section and design revision, out through the verification checks that claim to prove it, on to the tests and their coverage results, across to the signals and blocks on the affected interface, and ends at the bugs and waivers hanging off the same trace. A document store can return pages that mention the requirement; it cannot walk that chain. It is one of our [industrial ontology examples](https://codeatoms.ai/industrial-ontology-examples/), published as JSON.\n\nThe spec agent reads a new specification revision into requirements, and an engineer confirms each one before it is used; the rejection rate is a phase one gate, because a misread propagates into checks, coverage and impact lists. The check agent drafts tool-neutral assertions into version control, and the verification lead approves every one before it enters the regression, with an escalation to the senior verification expert after five working days. Nothing is trained into weights: expert lessons are kept as inspectable, citable records partitioned by need-to-know, which fine tuning could never be. Licences: GLM 5.3 carries a bespoke licence permitting commercial use, fine tuning and redistribution, BGE-M3 is MIT, PaddleOCR-VL 1.6 is Apache-2.0. The rollout is two phases and 18 scope items (15, then 3), and phase one is one block and one specification revision cycle.\n\nAppendix A prices the node at about 569,000 US dollars to own over three years (541,000 to 594,000), with power at the Saudi commercial electricity tariff. Renting the same eight cards on the deepest three-year commitment in AWS Middle East (UAE) is about 751,000, so ownership costs about three quarters of it, and about 2.00 million on demand, against which ownership costs a little over a quarter. Renting is a price reference only: no rented option sits inside the Kingdom on the day the prices were read, and the design records would cross the border.\n\nDesigned on CodeNinja Praxis, the CodeNinja Atoms platform for designing physical AI systems. The object model imports into Hyper Ontology. Paper, ontology and register: [https://codeatoms.ai/chip-design-ontology-saudi-arabia/](https://codeatoms.ai/chip-design-ontology-saudi-arabia/)\n\nOne of the CodeNinja Atoms [sovereign AI reference architectures](https://codeatoms.ai/sovereign-ai-reference-architectures/): every published design with its sector, country, compute and three-year cost.", "url": "https://wpnews.pro/news/system-design-for-physical-ai-a-chip-design-record-from-spec-to-tapeout", "canonical_source": "https://dev.to/umar_bilal_fd6e1f54398cec/system-design-for-physical-ai-a-chip-design-record-from-spec-to-tapeout-3mfm", "published_at": "2026-10-28 02:38:43+00:00", "updated_at": "2026-10-28 02:41:12.234093+00:00", "lang": "en", "topics": ["ai-agents", "ai-infrastructure", "mlops", "ai-tools", "ai-chips"], "entities": ["Muhammad Umar", "CodeAtoms", "Apache Kafka", "Keycloak", "Harbor", "GLM 5.3", "vLLM", "BGE-M3"], "also_reported_by": [], "alternates": {"html": "https://wpnews.pro/news/system-design-for-physical-ai-a-chip-design-record-from-spec-to-tapeout", "markdown": "https://wpnews.pro/news/system-design-for-physical-ai-a-chip-design-record-from-spec-to-tapeout.md", "text": "https://wpnews.pro/news/system-design-for-physical-ai-a-chip-design-record-from-spec-to-tapeout.txt", "jsonld": "https://wpnews.pro/news/system-design-for-physical-ai-a-chip-design-record-from-spec-to-tapeout.jsonld"}}