Speaking the Language of Physics: Introducing the First Instruction Set Architecture (ISA) for Dynamical System Hardware

Researchers have introduced DS-ISA, the first instruction set architecture for dynamical system hardware, aiming to standardize software interfaces for analog computing. The architecture, presented at ISCA 2026, enables efficient mapping of AI workloads onto physical systems that compute via natural energy minimization, potentially achieving over 1,000× efficiency gains over digital processors.

June 30, 2026 Research Speaking the Language of Physics: Introducing the First Instruction Set Architecture ISA for Dynamical System Hardware Written by: Editor’s Note: This post highlights foundational research on analog computing primitives accepted to ISCA 2026, conducted by Prof. Ang Li prior to joining Unconventional AI. At Unconventional AI, we are continuously exploring novel architectural paradigms to bypass the AI energy bottleneck; this deep dive explores how the broader industry can begin to standardize software interfaces for physical computing substrates. With the acceptance of this research, Ang Li will be formally inducted into the ISCA Hall of Fame at the conference this year. - To unlock the massive potential of emerging dynamical system hardware, the wider AI computing community needs a standardized way for software to “talk” to analog physics. - In an upcoming ISCA ’26 paper, my co-authors and I present an academic exploration of what this could look like: DS-ISA, the first Instruction Set Architecture designed specifically for continuous-time dynamical systems. - The paper’s proposed architecture explores powerful mechanisms for hardware sharing and “cascading” coupled dynamical systems, allowing one physical system to drive another for complex AI workloads. - While DS-ISA represents one proposed proof-of-concept rather than a definitive commercial product, it highlights the vital abstraction layer needed to eventually build automated compilers for future large-scale, dynamics-based AI hardware. The AI Energy Bottleneck and the Promise of Dynamics The AI industry is hurtling toward an energy wall. As models scale exponentially, the unsustainable energy cost of simulating neural networks on standard digital processing units is driving an industry-wide interest in novel computing paradigms. To unlock orders-of-magnitude efficiency leaps, researchers are increasingly exploring dynamical system hardware implemented with room-temperature, CMOS-compatible electronics. In a Dynamical System Unit DSU , coupled physical elements spontaneously interact and evolve toward low-energy equilibrium states within an energy landscape that embeds the targeted problem. The physical trajectory of the system and its final stabilized state represent nature’s spontaneous solution to that problem. This “intelligence-carrying” paradigm has the potential to deliver more than 1,000× performance and energy efficiency over conventional digital processors for AI applications. The Missing Link: We Need a Vocabulary for Physics Despite this tremendous potential, a major roadblock hinders the broad adoption of dynamical hardware: the absence of standardized instruction abstraction layers. Today, mapping high-level AI computational problems onto analog hardware relies on implementation-specific, ad hoc methods. Traditional computers rely on an Instruction Set Architecture ISA that tells the digital hardware exactly what to do, step by step, using discrete digital instructions. Because a DSU computes by leveraging the continuous physical progression of an interconnected analog system, sequential digital ISAs are fundamentally inadequate here. Without a formal programming model and a standardized vocabulary tailored to this unique computational paradigm, the computing community cannot build the essential software stacks, compilers, and runtimes needed to integrate dynamical system hardware into modern data centers. DS-ISA: An Instruction Set for the Physical World of Dynamics In an upcoming ISCA 2026 paper, my co-authors and I present a first-of-its-kind effort to establish the ISA for DSUs. Our research set out to answer a core architectural question: how can we cleanly bridge the gap between traditional digital host processors and continuous-time analog hardware? By analyzing execution patterns across a wide variety of DSU applications, our paper proposes a unified, composable load-lock-evolve-store execution model. Rather than forcing a rigid linear pipeline, our paper breaks dynamical computation down into five flexible, composable phases: Connect: Dynamically configure system connectivity to allocate resources. Load: Set initial states and parameters in the hardware components. Lock: Clamp boundary components to fixed values so their physical states remain stable. Evolve: Trigger the synchronous, collective physical evolution of all non-locked components. Store: Retrieve transient or stabilized states from the system. Our paper demonstrates that an entire dynamical unit can be orchestrated using a minimalist 9-instruction ISA. To manage the continuous-time physics, this model relies on a unique “ label-and-trigger ” mechanism: labeling commands pre-set the hardware lock masks, after which a dedicated evolution instruction acts as the trigger to unleash the physical dynamics simultaneously. Cascading Physics: High-Order and Coupled Dynamical Systems Modern AI is rarely a single feed-forward calculation; it involves deep, multi-layered dependencies. Therefore, any viable physics-driven accelerator and its accompanying ISA will eventually have to handle high-order computations where one dynamical system directly controls or feeds into another. To solve this, this effort explores mechanisms for “co-evolution with dependency” via a Cascading Node Evolution pattern. In this proposed microarchitecture, node groups are connected sequentially to form a physical pipeline. In a multi-layer machine learning model, for example, the equilibrium state reached by one evolving dynamical stage serves as the direct physical input that drives the evolution of the next cascading stage. This provides system designers with a concrete mathematical and architectural model for mapping layered neural networks directly onto coupled physical substrates. Sharing the Substrate: Maximizing Hardware Efficiency Because building large-scale physical processing units involves significant capital and silicon area, future architectures will likely require sophisticated multi-tenancy. Managing the potentially vast number of nodes and couplings required for large-scale AI introduces massive digital control complexity. To resolve this without suffocating the analog efficiency, the proposed microarchitecture draws inspiration from GPUs. Our method organizes nodes and couplings into discrete groups, allowing a single instruction to operate synchronously across an entire group in lockstep. To coordinate this, the controller employs a two-level masking scheme: inter-group masks handle macro-level synchronization, while intra-group masks selectively target individual elements for fine-grained configuration . This group-based approach yields great architectural flexibility. Using a Parallel Node Evolution pattern, the hardware can be dynamically partitioned to execute multiple independent tasks concurrently, such as running batched inference across different models side-by-side. Furthermore, our paper shows how fine-grained masking can reclaim scattered, unused “bubbles” of hardware to mitigate resource fragmentation, or be utilized by a runtime for wear-leveling to extend the operational lifespan of the silicon. Paving the Way for Large-Scale AI Hardware and Compilers Every year, the International Symposium on Computer Architecture ISCA serves as the premier proving ground for the ideas that will govern the next decade of computer science. The acceptance of this work into ISCA signals a pivotal consensus shift within the computer architecture community: physics-based AI accelerators are quickly maturing past the point of isolated circuit novelties, and urgently require formal computer science abstractions to sustain a thriving software ecosystem . By offering a concrete proof-of-concept for an ISA and its supporting digital controller, this research lays the foundation for constructing a complete DSU software stack. It proves that high-level applications can be systematically compiled down to the raw physics of room-temperature electronics, representing a vital step toward turning biology-scale energy efficiency from a laboratory triumph into the robust, scalable compute infrastructure of tomorrow.