Software to Silicon With RISC-V for Physical AI

EE Times moderated a panel with MIPS CEO Sameer Wasson and RISC-V International CEO Andrea Gallo on rethinking chip design for agentic AI. The discussion covered GlobalFoundries' acquisition of MIPS and Synopsys ARC Processor IP, RISC-V becoming the default ISA for new designs, and the shift to software-first architectures.

Nitin Dahad of EE Times moderates a panel with Sameer Wasson, CEO of MIPS, by GlobalFoundries, and Andrea Gallo, CEO of RISC-V International, for a conversation on how the industry must rethink chip design for agentic AI. Topics covered: • GlobalFoundries’ acquisition of MIPS and the recent acquisition of the Synopsys ARC Processor IP solutions business and what it means for customers • Why RISC-V is becoming the default ISA for new silicon designs • The shift to software-first, workload-optimized architectures Partner Content View All https://www.eetimes.com/category/sponsored-content/ By Christopher McGrady 06.22.2026 By Morten Block, Global Eng. Director, Segments and Technology go-to-market 06.17.2026 By Shanghai Yongming Electronic Co.,Ltd 06.16.2026 • How MIPS Atlas Explorer virtual platforms shortens time to revenue