SK Hynix, Sandisk unveil first standard for high bandwidth flash

SK Hynix and Sandisk unveiled the first standard specifications for high bandwidth flash (HBF), a next-generation memory technology designed to address supply chain constraints of high bandwidth memory (HBM). The specifications, developed under the Open Compute Project (OCP), support capacities up to 512 gigabytes across two stack configurations and bandwidth levels ranging from 0.4 to 3 terabits per second, using Universal Chiplet Interconnect Express (UCIe) to link with GPUs and CPUs. The consortium, which includes Google and Tenstorrent, aims to expand technical maturity and market acceptance, with first inference devices expected to sample around early 2027.

SK Hynix and Sandisk unveiled the first standard specifications for high bandwidth flash HBF , the next-generation alternative to supply chain-constrained high bandwidth memory. Revealed some six months after the pair kicked off a consortium to standardize the nascent technology via the Open Compute Project OCP , capacity specs cover up to 512 gigabytes across two stack configurations. Bandwidth levels are measured across three grades, outlining performance capabilities ranging from 0.4 to 3 terabits per second Tb/s . It also makes use of Universal Chiplet Interconnect Express UCIe , the open high-speed interconnection to interlink the memory hardware with accelerators including graphics processing units GPUs and central processing units CPUs . “With the rapid spread of AI applications, we are at a point where overall data processing structures must be redesigned,” said SK Hynix EVP and head of solution development Kim Chun-sung, adding, “Through HBF, SK Hynix will expand the boundaries between memory and storage and contribute to building new architectures that enhance overall system efficiency.” HBF was teased back in February 2025, with Sandisk contending that traditional HBM, which uses dynamic random-access memory DRAM at its core, cannot scale physically or economically. Instead, it argued that taking vertical stacking and packaging concepts used for high-bandwidth memory HBM and pairing them with NAND flash allows for more memory capacity while providing comparable levels of bandwidth – all while maintaining a similar price point. In conversation with SDxCentral https://www.sdxcentral.com/analysis/beyond-hbm-the-flash-memory-technology-that-could-reshape-ai-infrastructure/ back in May, Sandisk’s Cynthia Hsu said HBF was purpose-built for AI inference workloads, while also offering means to significantly reduce energy consumption for memory-intensive workloads. HBF development efforts were given a lift when Google engineers lauded it https://www.sdxcentral.com/news/ai-inference-crisis-google-engineers-on-why-network-latency-and-memory-trump-compute/ for potentially providing 10 times the memory capacity per node for inference workloads Google was listed as a participant in the HBF consortium per SK Hynix’s announcement, with Jeff Bezos and Samsung-backed AI chip firm Tenstorrent also on board. Following the launch of the first HBF standard, the memory chip makers said the consortium will work to further expand technical maturity and market acceptance “based on open collaboration.” “As agentic AI rapidly commercializes, the volume of data to process is surging alongside growing demands for higher speed and efficiency,” the announcement reads. “Recognizing that a single memory type cannot address these complex challenges, both speakers will present the necessity and future direction of a next-generation architecture based on tiered memory, a framework that connects and optimizes diverse memory types into a unified system.” The first inference devices powered by HBF are expected to sample around early 2027, Hsu outlined back in May, with the OCP collaboration allowing the pair to “move a little bit faster.” “You don't want to do this in a silo. And we're moving quite fast under OCP," she told SDxCentral . “You won't have to wait too long.”