{"slug": "sk-hynix-and-intel-explore-shared-memory-pools-to-ease-ai-bottlenecks", "title": "SK Hynix and Intel explore shared memory pools to ease AI bottlenecks", "summary": "SK Hynix presented a shared memory pool design, developed with Intel and other partners, at the Intel AI Summit in Seoul on November 12, 2026, moving high-capacity memory into dedicated racks that multiple GPU and CPU servers reach over Compute Express Link (CXL) and RDMA. In SK Hynix internal testing, remote CXL DRAM from a shared pool cut average time to first token on KV-cache-heavy inference from 80.76 seconds to 15.45 seconds, roughly an 81% reduction in first-token latency. SK Hynix Vice President Joo Young-pyo cited inefficiencies in attaching high-bandwidth memory directly to each GPU, and the company said the architecture will be validated with Intel, customers and other strategic partners starting from the system-design phase.", "body_md": "# SK Hynix and Intel explore shared memory pools to ease AI bottlenecks\n\nPhoto: Tara Winstead / Pexels\n\nThe memory maker's rack-scale design aims to let multiple AI servers draw from one large pool of memory as agentic AI workloads grow\n\nSK Hynix is working with Intel and other industry partners on a new way to feed AI servers. The idea is to stop giving every machine its own private stash of memory and let them share a common pool.\n\nThe push comes as agentic AI, the kind of software that runs multi-step tasks on its own, keeps raising demand for memory capacity and bandwidth.\n\n## What SK Hynix actually proposed\n\nSK Hynix presented the concept, called a **shared memory pool**, at the Intel AI Summit in Seoul on November 12, 2026.\n\nIn technical terms, the design moves high-capacity memory into dedicated racks. Multiple GPU and CPU servers can then reach that memory through high-speed interconnects such as Compute Express Link (CXL) and RDMA.\n\nCXL lets processors treat external memory as if it were nearby, while RDMA lets machines read each other’s memory without routing every request through the main processor.\n\nThe pooled racks would sit alongside existing server setups rather than replace them.\n\nSK Hynix Vice President Joo Young-pyo pointed to inefficiencies in the traditional approach, where high-bandwidth memory is attached directly to each GPU. He also credited progress to joint ecosystem development with partners.\n\n### AI, tech, and the markets they move—in one daily briefing.\n\nDaily. Free. Join 34,000+ readers across crypto, finance, and policy.\n\n## The KV cache problem, and an 81% answer\n\nThe design targets one specific headache: the KV cache. This is the working memory an AI model builds up as a conversation or task unfolds, and it grows quickly during multi-turn inference.\n\nSK Hynix’s internal testing put numbers on how costly that can be. Using eviction and recompute, the average time to first token came in at 80.76 seconds.\n\nWith remote CXL DRAM from a shared pool, that figure dropped to 15.45 seconds. That works out to approximately an 81% reduction in first-token latency.\n\nThese are internal results, though. SK Hynix said the architecture will be validated with Intel, customers and other strategic partners, starting from the system-design phase onward.\n\n## A partnership with history\n\nThis is not the first time the two companies have teamed up on server memory. In December 2025, SK Hynix became the first vendor to receive Intel Data Center certification for a 256 GB DDR5 RDIMM on the Xeon 6 platform.\n\nThat module delivered up to a 16% increase in inference performance. It also cut power consumption by approximately 18%.\n\nThe shared memory pool builds on that relationship and fits SK Hynix’s broader focus on memory-centric computing. The research framing positions Intel’s CPUs as orchestrators in agentic AI systems, coordinating the work while GPUs handle heavy computation and pooled memory holds the growing context.\n\n**Disclosure:** This article was edited by Diego Almada Lopez. For more information on how we create and review content, see our [Editorial Policy](https://cryptobriefing.com/editorial-policy/).", "url": "https://wpnews.pro/news/sk-hynix-and-intel-explore-shared-memory-pools-to-ease-ai-bottlenecks", "canonical_source": "https://cryptobriefing.com/sk-hynix-intel-shared-memory-pool-ai/", "published_at": "2026-11-13 07:07:28+00:00", "updated_at": "2026-11-13 07:21:57.713311+00:00", "lang": "en", "topics": ["ai-infrastructure", "ai-chips", "ai-agents", "artificial-intelligence"], "entities": ["SK Hynix", "Intel", "Joo Young-pyo", "Compute Express Link", "RDMA", "Intel AI Summit", "Xeon 6"], "also_reported_by": [], "alternates": {"html": "https://wpnews.pro/news/sk-hynix-and-intel-explore-shared-memory-pools-to-ease-ai-bottlenecks", "markdown": "https://wpnews.pro/news/sk-hynix-and-intel-explore-shared-memory-pools-to-ease-ai-bottlenecks.md", "text": "https://wpnews.pro/news/sk-hynix-and-intel-explore-shared-memory-pools-to-ease-ai-bottlenecks.txt", "jsonld": "https://wpnews.pro/news/sk-hynix-and-intel-explore-shared-memory-pools-to-ease-ai-bottlenecks.jsonld"}}