{"slug": "side-channel-protections-in-hardware-implementations-of-pqc-ml-kem-verification", "title": "Side-Channel Protections in Hardware Implementations of PQC ML-KEM Verification", "summary": "Researchers found that FPGA implementations of ML-KEM decapsulation verification leak side-channel information even with higher-order masking, enabling full secret-key recovery. The study compared unprotected, hash-based, and masked designs on microcontrollers and FPGAs, showing that parallelized FPGA processing introduces first-order leakage. These results highlight ongoing challenges in securing post-quantum cryptography against physical attacks.", "body_md": "# Computer Science > Cryptography and Security\n\n[Submitted on 30 Jun 2026]\n\n# Title:Exploring Side-Channel Protections in Hardware Implementations of PQC ML-KEM Verification\n\n[View PDF](/pdf/2606.31681)\n\n[HTML (experimental)](https://arxiv.org/html/2606.31681v1)\n\nAbstract:As ML-KEM is adopted as a post-quantum cryptographic standard, resilience against physical side-channel attacks has become essential. Among the constituent steps, the decapsulation Fujisaki-Okamoto (FO) verification is particularly vulnerable to side-channel power and electromagnetic (EM) analysis. In this work, we focus on common FPGA-based implementations and examine their side-channel vulnerabilities, and compare them with those of microcontroller implementations. Three verification implementations, unprotected, hash-based (first-order), and higher-order masked, are evaluated for side-channel security on both a microcontroller and an FPGA. While FPGAs offer higher speed and parallelism, they often exhibit stronger side-channel leakage, especially in high bandwidth configurations. The higher-order masked designs still leak information about the underlying data due to hardware-level effects and data-dependent processing. Our experiments show that their parallelized processing on FPGAs introduces sufficient first-order leakage for full secret-key recovery. These results underscore the persistent challenge of securing PQC algorithms in performance-constrained and parallelized hardware environments.\n\n### References & Citations\n\nLoading...\n\n# Bibliographic and Citation Tools\n\nBibliographic Explorer\n\n*(*[What is the Explorer?](https://info.arxiv.org/labs/showcase.html#arxiv-bibliographic-explorer))\nConnected Papers\n\n*(*[What is Connected Papers?](https://www.connectedpapers.com/about))\nLitmaps\n\n*(*[What is Litmaps?](https://www.litmaps.co/))\nscite Smart Citations\n\n*(*[What are Smart Citations?](https://www.scite.ai/))# Code, Data and Media Associated with this Article\n\nalphaXiv\n\n*(*[What is alphaXiv?](https://alphaxiv.org/))\nCatalyzeX Code Finder for Papers\n\n*(*[What is CatalyzeX?](https://www.catalyzex.com))\nDagsHub\n\n*(*[What is DagsHub?](https://dagshub.com/))\nGotit.pub\n\n*(*[What is GotitPub?](http://gotit.pub/faq))\nHugging Face\n\n*(*[What is Huggingface?](https://huggingface.co/huggingface))\nScienceCast\n\n*(*[What is ScienceCast?](https://sciencecast.org/welcome))# Demos\n\n# Recommenders and Search Tools\n\nInfluence Flower\n\n*(*[What are Influence Flowers?](https://influencemap.cmlab.dev/))\nCORE Recommender\n\n*(*[What is CORE?](https://core.ac.uk/services/recommender))# arXivLabs: experimental projects with community collaborators\n\narXivLabs is a framework that allows collaborators to develop and share new arXiv features directly on our website.\n\nBoth individuals and organizations that work with arXivLabs have embraced and accepted our values of openness, community, excellence, and user data privacy. arXiv is committed to these values and only works with partners that adhere to them.\n\nHave an idea for a project that will add value for arXiv's community? [ Learn more about arXivLabs](https://info.arxiv.org/labs/index.html).", "url": "https://wpnews.pro/news/side-channel-protections-in-hardware-implementations-of-pqc-ml-kem-verification", "canonical_source": "https://arxiv.org/abs/2606.31681", "published_at": "2026-07-01 08:43:24+00:00", "updated_at": "2026-07-01 09:21:23.034642+00:00", "lang": "en", "topics": ["ai-safety", "ai-research", "ai-chips"], "entities": ["ML-KEM", "Fujisaki-Okamoto", "FPGA"], "alternates": {"html": "https://wpnews.pro/news/side-channel-protections-in-hardware-implementations-of-pqc-ml-kem-verification", "markdown": "https://wpnews.pro/news/side-channel-protections-in-hardware-implementations-of-pqc-ml-kem-verification.md", "text": "https://wpnews.pro/news/side-channel-protections-in-hardware-implementations-of-pqc-ml-kem-verification.txt", "jsonld": "https://wpnews.pro/news/side-channel-protections-in-hardware-implementations-of-pqc-ml-kem-verification.jsonld"}}