Samsung unveils memory road map at Semicon Taiwan

Samsung Electronics unveiled a next-generation memory strategy called 'CUBE' at Semicon Taiwan 2026, betting on 3D architectures to boost capacity, bandwidth, and energy efficiency for AI workloads. The company targets HBM5 with twice the performance of HBM4E, zHBM with eight times the performance, and zNAND-O with 10 times the bit density of DRAM, with sampling planned for 2028. Samsung leads the DRAM market with a 39% revenue share in Q2, according to Counterpoint Research, and the NAND flash market with a 29.3% share, per TrendForce.

Chipmaker turns to 3D memory to boost capacity, bandwidth and efficiency for AI Samsung Electronics on Tuesday unveiled a next-generation memory strategy at Semicon Taiwan 2026, betting on 3D architectures to boost capacity, bandwidth and energy efficiency as artificial intelligence workloads place growing demands on memory systems. Choi Jang-seok, head of the memory product planning team at Samsung Electronics, presented the road map in a keynote speech at the Memory Executive Summit in Taipei, a day before the main Semicon Taiwan exhibition opened. Samsung calls the strategy “CUBE,” short for capacity, utilization, bandwidth and efficiency. At its core is a move toward vertically integrated memory structures that can increase capacity without taking up more board space. “We will no longer be constrained by the printed circuit board area,” Choi said. “By expanding vertically, we can increase memory capacity without increasing the board footprint.” Samsung is also working to optimize how logic and memory are arranged within 3D structures to reduce processing delays. “3D is not simply about stacking. The key is how each layer is utilized,” he said. Shorter connections between dies could also sharply improve data-transfer speeds. “By dramatically shortening the distance between dies, we can create a vertical highway and substantially improve bandwidth,” Choi said. Efficiency is another key focus as AI systems consume more power and generate more heat. “The ultimate goal of 3D is to reduce the energy required to move a single bit of data,” he said. The strategy extends Samsung’s high-bandwidth memory road map beyond current-generation products. Samsung’s eighth-generation HBM, HBM5, is under development with targets of twice the performance of HBM4E, 20 percent higher performance per watt and 20 percent lower thermal resistance. Samsung is also developing zHBM, which aims for eight times the performance of HBM4E and three times the performance per watt, while cutting thermal resistance by 75 to 90 percent. zNAND-O, a NAND flash solution, is designed to meet the massive capacity needs of large language models while offering faster data access than conventional NAND. Samsung is targeting 10 times the bit density of DRAM and seven times the read bandwidth and power efficiency of NAND, with sampling planned for 2028. The push comes as Samsung leads both major memory markets. Market tracker Counterpoint Research put Samsung’s global DRAM revenue share at 39 percent in the second quarter, ahead of SK hynix at 26 percent and Micron Technology at 25 percent. Samsung also led the NAND flash market with a 29.3 percent share, according to TrendForce, as growing demand for enterprise SSDs from AI servers helped lift its second-quarter NAND revenue. Samsung said it plans to use its technology and manufacturing scale to meet growing demand across conventional memory as well as high-value AI products such as HBM and enterprise SSDs. yeeun@heraldcorp.com