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Ryzen AI Halo - USB4 Clustering with RDMA - Testing Notes

A developer testing USB4 clustering between a 12th gen Intel system and AMD Strix Point found that a kernel update on AlmaLinux enabled a dual-lane connection, boosting bandwidth from Intel to Strix Point to 22.7 Gbit/s, while the reverse direction remained at 11.7 Gbit/s. The author notes that Strix Point's USB4 controller can support dual-lane inter-domain connections, but it is finicky, and Windows' virtual network adapter still reports 20 Gbit/s regardless of the actual configuration.

read2 min views1 publishedAug 17, 2026

Aaand, how fast one can turn out to be wrong…

I just rebooted with a new kernel update on my AlmaLinux system and now, I actually get a dual-lane connection from 12th gen Intel to AMD Strix Point (Strix Point still running Windows).

Highest bandwidth 12th gen → Strix Point: barely 22.7 Gbit/s, but > 20 Gbit/s.

Strix Point → 12th gen still at 11.7 Gbit/s max.

No idea what actually changed, I mainly rebooted to get the debug logging of the thunderbolt kernel modules on to get better logging of why and when it fails the bonding and now it works.

So, I am happily wrong: appearently, Strix Point CAN do dual lane inter-domain. It just seems super finicky, because this is the first time its working. Strix Halo controllers may be slightly different from the Strix Point ones, as they have UHBR20 support on Strix Halo, but only UHBR10 with Strix Point. Though unsure if that is a GPU-side limitation or an actual small difference in USB4 controller hardware.

I can also confirm, Windows will stick to the 20Gbit/s rating of the virtual network adapter, so that number sadly seems hardcoded and cannot be used to quickly figure out what connection config one got and if one is hitting software bottlenecks or hardware bottlenecks.

That is a new one for me, I have not heard anybody speak of anything like that.

Full-featured USB-C is designed to have 8 high speed conductors, but they are in those 4 differential pairs. And symmetric USB4 connections are using 2 wire-pairs in each direction. So that is already using all of them. Only the single-lane config would leave half of them unused.

If one goes the more crazy route of the now defunct VirtualLink from Nvidia, one can maybe repurpose the USB2 wire pairs for another 2 wire-pairs, but I am still not getting to 8 (Nvidia used this to put 2 USB3 wire-pairs onto those USB2 pins to keep all 4 high-speed wire-pairs available for full DP with 4 lanes). But that is very much not standard, as a) the USB2 wires are not normally designed for those higher speeds and also because while the USB2 pins are symmetric and exist double, the conductors in a USB-C cable are not (socket needs to support both sets of USB2 wires, but is allowed to short both sets together or switch between them, the cable is only supposed to have the one wire-pair on the primary sides of its connectors and other side be unconnected).

So I do not know see, how 8 wire-pairs, let alone lanes in the USB sense (meaning bidirectional) are possible. If I had to guess, you only get to 8 “whatever” with some creative counting and throwing all different wire-types together. Or that was just the wire-count. But everything high-speed is done in differential pairs anyway…

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