RISC-V Targets Data Centers, Edge AI, Space

RISC-V International announced at the RISC-V Summit Europe 2026 in Bologna that its open-standard instruction set architecture has matured beyond microcontrollers and now targets data centers, edge AI, and space exploration markets. CEO Andrea Gallo said the architecture is poised for major commercial growth, with the SHD Group projecting RISC-V could capture 33.7% market share across all hardware segments by 2031. The ratification of the RISC-V Server Platform Specification 1.0, based on the RVA23 profile, has standardized hardware and driven a surge in high-performance server-class chips from companies including SiFive, Akeana, and Epic Semi.

BOLOGNA, Italy — For years, RISC-V open-standard instruction set architecture worked quietly behind the scenes, mostly appearing in microcontrollers, hard drives, and specialized industrial applications. But at this week’s RISC-V Summit Europe 2026 https://riscv-europe.org/summit/2026/ in Bologna, the message to the global tech community was unequivocal: The architecture has matured and now targets data centers, edge AI, and space exploration markets. “RISC-V is now,” said Andrea Gallo, CEO of RISC-V International, during his opening keynote address to a full auditorium. Gallo’s speech showed that RISC-V is close to major commercial growth. According to the SHD Group, RISC-V https://theshdgroup.com/market-reports/ could reach 33.7% market share across all hardware segments by 2031. This growth is especially visible in edge computing and data centers, with markets expected to top $45 billion and $70 billion by the end of the decade. The hardware ecosystem is booming, as startups such as SiFive and Axelera have raised $650 million together, and big companies such as Microsoft are joining as top board members. View All https://www.eetimes.com/category/sponsored-content/ Year of RVA silicon in the data center A key moment for RISC-V’s use in business came with the official ratification of the RISC-V Server Platform Specification 1.0 https://docs.riscv.org/reference/server-soc/ attachments/riscv-server-soc.pdf , based on the RVA23 profile https://riscv.org/blog/risc-v-announces-ratification-of-the-rva23-profile-standard/ , ratified in 2024. This important step standardizes the hardware, bringing industry-standard boot systems and runtime services, such as UEFI and ACPI 6.6 support https://uefi.org/specs/ACPI/6.6/ , directly to RISC-V. It ensures that system software runs smoothly across different server hardware. “It’s really important because it’s bringing industry standards to RISC-V,” Gallo noted in an interview with EE Times following his keynote. “At the same time, it’s the industry standards that are supporting RISC-V because the ACPI 6.6 officially supports RISC-V now.” This strict standardization is already driving a surge in high-performance chips. Called the “year of the RVA silicon,” 2026 is seeing many companies launch new server-class processors. Both large companies and startups are releasing powerful hardware, such as the SiFive Performance P870D with up to 128 cores, Akeana’s Alpine Test Chip, and NextSilicon’s Arbel server-grade CPU. Epic Semi has launched its Contrail AIX, a superchip that blends 32 RISC-V processor cores with 16 built-in AI cores, reaching up to 75 TOPS. “The server platform is the completion of the first phase,” Gallo explained during the interview. “Starting from RVA23, the server SoC, and then the server platform. And then this incredible number of RVA23 high-performance chips are coming out all this year. This is incredibly exciting for us.” For hyperscalers and data center operators, RISC-V is a strong alternative to proprietary architectures such as ARM and x86, effectively mitigating the risk of single-vendor lock-in. “The market is so large that there’s room for everyone,” Gallo said. “So it’s not that one is displacing the other, but there’s enough room for everyone for RISC-V to grow into the market.” He stressed that having choices is important for multinational companies and governments working on digital sovereignty. “RISC-V is bringing freedom of choice and freedom from a single vendor,” Gallo added. Big software companies have noticed this change. Canonical’s new Ubuntu 26.04 LTS operating system now fully supports RVA23, making it easier for enterprise teams to manage data centers with diverse hardware. Addressing physical AI at the edge Enterprise servers are a huge market, but the rise of AI is just as transformative. Gallo sees the future going beyond text and image recognition, toward “physical AI” that interacts directly with the real world. “The evolution that we see is that AI initially was inference, so it was recognizing,” Gallo told EE Times. “Then it became agentic, making decisions. And the physical means that you are also activating those decisions in the physical world.” To make physical AI work—whether in a robot adjusting its balance or in remote sensors deployed in the Amazon rainforest—the hardware must use very little power. RISC-V does this with advanced vector and matrix extensions, letting complex AI algorithms run on the same core that handles control software and the operating system. This design approach removes the need to constantly transfer data and weights to a separate neural processing unit, avoiding a slow, power-hungry process known as “memcopy.” “You don’t do memcopies to transfer the data, the weights from the CPU to the NPU, but everything is done on the same core,” Gallo said. “Memcopy means latency because it takes time, and memcopy means power consumption.” By removing this internal data-transfer problem, RISC-V greatly reduces power consumption and enables much smaller chips. This advantage was clear in Beijing, where a humanoid robot using SpacemiT’s K3 RISC-V processor finished a half-marathon. In Brazil, researchers at São Paulo University are using locally made, battery-powered RISC-V microcontrollers to build an “Internet of Trees.” This mesh network can automatically detect illegal logging and forest fires. Reaching the final frontier in space exploration Beyond Earth applications, RISC-V is becoming a key part of the next generation of spaceflight computers. Space is harsh, requiring microprocessors that are highly radiation- and fault-resistant. Historically, the aerospace industry relied heavily on legacy SPARC-based architectures, but an industry-wide pivot to RISC-V is now well underway. To organize this effort, a special RISC-V Space Special Interest Group https://riscv.atlassian.net/wiki/spaces/SPC/overview started at the end of 2025, chaired by representatives from the European Space Agency https://www.esa.int/ and E4 Computing. The group was created because the industry needed to adapt the open architecture for space. “Everyone had some questions,” Gallo recalled from a previous space workshop. “How do we configure RISC-V at best for the lunar lander? Or how do we configure RISC-V at best for cloud processing on a satellite? How do we properly isolate the software workloads on a satellite?” Now, the group brings together experts from NASA, Microchip, SiFive, and Frontgrade Gaisler to write strict standards and white papers for these specialized space missions. Major hardware projects are already underway. NASA is working with Microchip and SiFive to test a high-performance spaceflight processor, and the European Commission’s COSMIC7 project is building a 7-nm RISC-V chip designed just for orbit. For older aerospace suppliers such as Frontgrade Gaisler, now moving from SPARC-based LEON processors to new RISC-V-based NOEL chips, the open nature of RISC-V is the main attraction. Aerospace groups need full transparency in their hardware to get safety certifications. “There’s a strong requirement for publicly available specifications for them to be able to own the product, to own their destiny,” Gallo said. “RISC-V is the only alternative to natural evolution.” Mature ecosystem and commercial success The RISC-V ecosystem is evolving quickly, with both strong startup growth and increasing participation from major companies. Gallo sees this as proof that the architecture works. “When you have such successful acquisitions, it means that those companies were doing things really right,” Gallo said, noting the steady stream of new startups launching high-performance chips. The developer community is just as enthusiastic. At RISC-V Summit Europe 2026, developer workshops sold out, with 120 engineers working on hands-on debugging and advanced hardware design challenges. People no longer see RISC-V as just an academic project or a simple embedded controller. The open architecture has clearly matured, supported by standard specs, strong corporate support, and a large software ecosystem. It is now ready for applications ranging from enterprise computing and edge AI to the demanding environment of spaceflight. As Gallo said at the RISC-V Summit Europe 2026, the tech industry no longer needs to ask when RISC-V will arrive. It is already here. See also: RISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware https://www.eetimes.com/risc-v-summit-europe-2026-industry-and-academia-unite-in-bologna-to-advance-open-hardware/ When Arm Meets RISC-V: SiPearl, Semidynamics to C https://www.eetimes.com/when-arm-meets-risc-v-sipearl-semidynamics-to-co-develop-sovereign-ai-platform/ o-Develop Sovereign AI Platform https://www.eetimes.com/when-arm-meets-risc-v-sipearl-semidynamics-to-co-develop-sovereign-ai-platform/ Alibaba Launches XuanTie C950 CPU for Agentic AI https://www.eetimes.com/alibaba-launches-xuantie-c950-cpu-for-agentic-ai/