Rethinking the Logic-Routing Tradeoff in FPGAs

Efinix has launched the Titanium Edge family of FPGAs for edge AI applications, based on soft or hard RISC-V cores with AI instruction extensions. The company's XLR logic cell dynamically reconfigures between logic and routing functions, reducing die area and power consumption by half compared to top-performing FPGAs. The new family adds SEU protection, post-quantum security, and support for up to 2.5 Gb/s MIPI interfaces, with select models co-packaged with HyperRAM for on-chip storage of AI inference data.

Efinix has launched a family of FPGAs aimed at edge AI applications, based on soft or hard RISC-V cores with instruction extensions for AI. The Titanium Edge family outperforms other FPGAs on performance, power, and economics, Bob Beachler, corporate VP of marketing and corporate development at Efinix, told EE Times. Efinix’s secret sauce is in its XLR logic cell. Traditional FPGAs have to balance how much silicon space is dedicated to routing and how much is available for logic; FPGA companies https://www.embedded.com/powering-the-future-of-on-device-ai-with-fpgas/ have made logic blocks more complex to minimize routing, since routing is expensive in terms of area, Beachler said. But once data has to move outside a logic element, it has to be driven down wires, which consumes power and contributes to thermal stress. “For some sets of designs, the ratio between logic and routing is wrong, you either have too much routing and waste silicon area, or you have too many logic elements that you can’t route to,” he said. “In a typical FPGA design, you may have places that have lots of routing but are very congested, and some areas of the design that don’t need as much routing as they are very sparse.” Efinix’s key IP is around enabling its logic cell to do either logic or routing XLR stands for exchangeable logic and routing . View All https://www.eetimes.com/category/sponsored-content/ “In that way, we can dynamically determine how much routing or how much logic goes into each area of a given design,” Beachler said. Software determines how much logic and routing is required, and where. “This is very efficient,” Beachler said. “This technology can have similar or greater performance than top-performing FPGAs, but at half the power and half the die area.” The company has already commercialized this technology in its Titanium family, which is aimed at applications that require more processing power. The new Titanium Edge family has the same basic architecture with a few tweaks. Static power consumption has been reduced by half compared to earlier Titanium parts. Efinix has added single-event upset SEU , post-quantum security, and higher-speed I/O. Enhanced high-speed interfaces support up to 2.5 Gb/s MIPI interfaces for image sensors. MIPI blocks in earlier Titanium parts were hardened blocks, but since the FPGA fabric is fast enough, it can be run as a soft controller, Beachler said. “This gives customers more flexibility about where they put their MIPI interfaces,” he said. Up to eight lanes of MIPI are supported. This is key to applications such as robotics, where each hand or finger contains multiple sensors. Competitive landscape AI co-processors have had limited success in the edge market, Beachler said, while SoC solutions with on-board NPUs have fared better. Successful SoC solutions typically include other accelerators such as image signal processors or video codecs. “I have customers who use both FPGAs and off-the-shelf SoCs ,” he said. “If they get a new sensor that can’t go directly into the SoC or something more custom is required, they’ll use an FPGA instead. We have IP blocks that can run video encode and decode, for example, and it will work out a little more expensive than the SoC, but it will give the designers flexibility.” FPGAs are sometimes used as front-end processing before handing off to an SoC, Beachler said. For example, humanoid robots may require processing close to the sensor before passing metadata to a bigger processor or “brain” elsewhere in the body. Co-packaged HyperRAM Efinix will offer some members of the Titanium Edge family co-packaged with HyperRAM a DRAM die that behaves like SRAM . This can be used to store intermediate weights during AI inference or data, such as intermediate video frames. Area is drastically reduced by moving memory into the same package as the FPGA, Beachler said. “We buy the dies from Winbond, and we put them all in the package so customers can get to market faster, and they don’t have to worry about sourcing memory, which can be a big issue,” he said. “Customers love it.” Some Titanium Edge parts have two HyperRAMs, some have one. Other FPGA makers cannot stack memory dies on the FPGA die because they burn too much energy; Efinix’s energy efficiency directly enables 3D stacking, Beachler said. Some parts in the Titanium Edge series are already shipping, with the rest of the family expected to become available by the end of 2026. See also: RISC-V Exceeding Expectations in AI, China Deployment https://www.eetimes.com/risc-v-exceeding-expectations-in-ai-china-deployment/ GPUs Dominate AI Compute, FPGAs Move Into the AI Data Path https://www.eetimes.com/gpus-dominate-ai-compute-fpgas-move-into-the-ai-data-path/