Reinforcement learning for hardware acceleration and system-level optimization on FPGA and integrated-circuit platforms: A survey

A new arXiv survey (2610.28699v1) reviews more than 100 studies on reinforcement learning implementations across field-programmable gate array (FPGA) and integrated-circuit (IC) platforms, organizing the literature by RL family from model-based Markov decision processes through deep RL, actor-critic, policy-gradient and multi-agent approaches. The survey classifies studies by abstraction level, hardware realization strategy and application domain, comparing resource utilization, latency, throughput, power consumption and reported performance gains across acceleration, reconfigurable architectures, energy-aware control and system-level optimization. The authors position the work as a unified reference spanning both reconfigurable and fixed hardware, identifying recurring architectural patterns, practical limitations and open research directions for RL-driven hardware systems.

arXiv:2610.28699v1 Announce Type: new Abstract: Reinforcement learning RL enables adaptive and autonomous decision-making in embedded, edge, and heterogeneous computing systems. Field-programmable gate arrays FPGAs and integrated circuits ICs offer low latency, energy efficiency, and architectural flexibility for RL deployment, while introducing challenges in resource constraints, implementation complexity, and hardware-algorithm co-design. This review surveys more than 100 studies on RL implementations across FPGA and IC platforms, emphasizing architectures, implementation strategies, performance evaluation, and applications. The literature is organized by RL family, including model-based Markov decision processes, classical value-based methods, deep RL, actor-critic, policy-gradient, and multi-agent approaches. We further classify studies by abstraction level, hardware realization strategy, and application domain, examining how RL algorithms map onto reconfigurable and fixed hardware. Unlike surveys restricted to particular algorithms or platforms, this work provides a unified analysis of FPGA and IC implementations, covering acceleration, reconfigurable architectures, energy-aware control, and system-level optimization. Comparative assessments consider resource utilization, latency, throughput, power consumption, and reported performance gains. Finally, we identify recurring architectural patterns, practical limitations, open challenges, and research directions for efficient RL-driven hardware systems. The survey offers a consolidated reference for researchers developing and evaluating RL solutions on specialized hardware.