# QwenGPU: A functioning, deterministic SIMT GPU inside Qwen3.5 > Source: > Published: 2026-11-02 16:45:27+00:00 Meet qwenGPU: Qwen3.5-2B with a SIMT GPU inside its weights, 45 compiled layers in front of Qwen’s own, using its Gated DeltaNet layers as registers and memory. It runs real CUDA in its forward passes. The host compiles the kernel to PTX and loads it, then the model writes every step of the launch itself: every register, branch and memory write. The GPU has 4-lane warps, a 4-stage pipeline, 15 registers per lane and 126 words of global memory, all held in DeltaNet state. Qwen generates each launch token by token, each record running one machine block for one warp.