QwenGPU: A functioning, deterministic SIMT GPU inside Qwen3.5

A project called QwenGPU has embedded a functioning, deterministic SIMT GPU inside the weights of Qwen3.5-2B, adding 45 compiled layers in front of Qwen's own and using the model's Gated DeltaNet layers as registers and memory. The system runs real CUDA in its forward passes: the host compiles the kernel to PTX and loads it, after which the model writes every step of the launch itself, including every register, branch and memory write. The GPU has 4-lane warps, a 4-stage pipeline, 15 registers per lane and 126 words of global memory held in DeltaNet state, with Qwen generating each launch token by token and each record running one machine block for one warp.