(PR) XCENA Details MX1 Architecture Integrating Memory Expansion and Near-Memory Computing at Hot Chips 2026

XCENA, a semiconductor company developing memory-centric computing solutions for AI infrastructure, presented the architecture and measured performance of its MX1 computational CXL memory architecture at the Hot Chips 2026 Memory session. Presented by Chief Product Officer Harry Kim, MX1 combines large-scale memory expansion, SSD-backed capacity, and programmable near-memory computing in a single CXL Type 3 device to address memory constraints in AI infrastructure by offloading memory-bound operations like vector search and KV-cache retrieval.

XCENA, a semiconductor company developing memory-centric computing solutions for AI infrastructure, today presented the architecture and measured performance of MX1, its computational CXL memory architecture, during the Hot Chips 2026 Memory session. Presented by Harry Kim, Chief Product Officer of XCENA, the session examined how MX1 combines large-scale memory expansion, SSD-backed capacity and programmable near-memory computing in a single CXL Type 3 device to address the growing memory constraints of AI infrastructure. The MX1 presentation was selected through the Hot Chips program committee's technical review process. As AI models continue to grow, system performance is increasingly constrained by memory capacity, data movement and the economics of high-bandwidth memory scaling rather than compute alone. MX1 is designed to complement CPUs, GPUs and AI accelerators by expanding memory capacity and offloading selected memory-bound operations—including vector search, KV-cache retrieval and data preprocessing—so host processors can focus on compute-intensive inference.