{"slug": "ppaplace-differentiable-cross-stage-objectives-for-chip-placement-optimization", "title": "PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization", "summary": "PPAPlace, a timing-driven differentiable surrogate developed by researchers, improves chip placement by predicting post-route power, performance, and area (PPA) from macro and standard-cell placements, achieving average worst negative slack (WNS) and total negative slack (TNS) improvements of 22% and 51% over the hierarchical baseline on five ChiPBench test circuits. The method, which uses post-global-routing labels and combines graph attention with spatial convolution, addresses the near-zero correlation between half-perimeter wirelength (HPWL) and post-route timing metrics observed in six AI placers. The code is available at https://github.com/ValleyC/PPAPlace.", "body_md": "arXiv:2608.13790v1 Announce Type: new\nAbstract: Macro placement significantly affects a chip's post-route performance, power, and area (PPA). Most placement methods optimize half-perimeter wirelength (HPWL) as the primary objective. However, recent benchmarking shows a near-zero correlation between HPWL and post-route timing metrics such as the worst negative slack (WNS) and total negative slack (TNS). As a result, all six evaluated artificial intelligence (AI) placers degraded PPA relative to the hierarchical baseline. Recent efforts have tried to train cross-stage predictors to close this gap. However, existing methods focus on macro-only representations and use pre-route metrics as training labels. A label fidelity study of ten circuits at four design flow stages reveals that HPWL and pre-route timing poorly reflect final post-route timing rankings. In contrast, post-global-routing achieves the best balance between final timing fidelity and label generation cost-effectiveness. Based on this finding, PPAPlace is a timing-driven differentiable surrogate predicting post-route PPA from macro and standard-cell placements. The surrogate is a dual-stream predictor that combines graph attention over the chip netlist with spatial convolution over the placement grid. It is trained on post-global-routing labels. The predicted WNS and TNS gradients flow end-to-end back to cell coordinates. PPAPlace exploits these gradients in two ways: as a co-objective injected into an analytical placer's optimization loop (PPAPlace-CoOpt), and as a post-placement refinement step that adjusts macro positions via projected gradient descent (PPAPlace-Refine). On five ChiPBench test circuits excluded from training, PPAPlace improves average WNS and TNS by 22\\% and 51\\% over the hierarchical baseline while preserving power and routability, using the same predictor without test-circuit retraining. Code is available at https://github.com/ValleyC/PPAPlace.", "url": "https://wpnews.pro/news/ppaplace-differentiable-cross-stage-objectives-for-chip-placement-optimization", "canonical_source": "https://arxiv.org/abs/2608.13790", "published_at": "2026-08-17 04:00:00+00:00", "updated_at": "2026-08-17 04:13:12.012185+00:00", "lang": "en", "topics": ["artificial-intelligence", "machine-learning", "ai-research"], "entities": ["PPAPlace", "ChiPBench", "arXiv"], "alternates": {"html": "https://wpnews.pro/news/ppaplace-differentiable-cross-stage-objectives-for-chip-placement-optimization", "markdown": "https://wpnews.pro/news/ppaplace-differentiable-cross-stage-objectives-for-chip-placement-optimization.md", "text": "https://wpnews.pro/news/ppaplace-differentiable-cross-stage-objectives-for-chip-placement-optimization.txt", "jsonld": "https://wpnews.pro/news/ppaplace-differentiable-cross-stage-objectives-for-chip-placement-optimization.jsonld"}}