{"slug": "placereasoner-beta-reasoning-driven-macro-placement-and-benchmarking", "title": "PlaceReasoner-Beta: Reasoning-Driven Macro Placement and Benchmarking", "summary": "PlaceReasoner-Beta, a verifier-guided multi-agent framework from the authors of arXiv:2609.21263v1, reformulates VLSI macro placement as a closed-loop reasoning problem using a vision-language model planner, a geometric verifier, a physical verifier, and a post-route optimizer. On the accompanying open benchmark PlaceReasoner-Bench — 8 designs at two aspect ratios for 16 tasks evaluated by routed PPA and DRC — the framework achieved the best timing among DRC-clean methods on all square tasks, cutting post-route TNS by 61.2% at 1:1 and 53.0% at 2:1 versus the classical baseline field, while also shortening routed wirelength on most designs despite never explicitly optimizing it.", "body_md": "arXiv:2609.21263v1 Announce Type: new \nAbstract: Automated macro placement remains a fundamental challenge in VLSI physical design. Despite decades of research, existing approaches predominantly optimize hand-crafted proxy objectives, such as estimated wirelength, and typically produce placements through one-shot numerical optimization, limiting their ability to incorporate visual layout context, codified design expertise, and downstream physical-design feedback in a unified loop. We present PlaceReasoner-Beta, a verifier-guided multi-agent framework that reformulates macro placement as a closed-loop reasoning problem rather than black-box optimization. A vision-language model (VLM) planner generates candidate placements from the floorplan image, macro specifications, and connectivity structure; a geometric verifier enforces physical legality and expert placement principles; a physical verifier refines candidates using early implementation feedback; and a post-route optimizer further improves promising layouts using final PPA. To enable reproducible evaluation, we introduce PlaceReasoner-Bench, a fully open end-to-end benchmark built from open RTL designs, EDA tools, and technology libraries. It comprises 8 designs at two aspect ratios, yielding 16 tasks with fixed floorplans and I/O assignments, so methods differ only in macro positions and orientations and are evaluated using routed PPA and DRC rather than pre-route proxies. Across the benchmark, PlaceReasoner-Beta achieves the best timing among DRC-clean methods on all square tasks, reducing post-route TNS by 61.2% at 1:1 and 53.0% at 2:1 relative to the classical baseline field. It also shortens routed wirelength on most designs despite never explicitly optimizing it, demonstrating that reasoning over spatial structure under physical-design feedback can improve end-to-end layout quality beyond proxy-objective optimization.", "url": "https://wpnews.pro/news/placereasoner-beta-reasoning-driven-macro-placement-and-benchmarking", "canonical_source": "https://arxiv.org/abs/2609.21263", "published_at": "2026-09-21 04:00:00+00:00", "updated_at": "2026-09-21 04:26:23.442754+00:00", "lang": "en", "topics": ["machine-learning", "ai-agents", "ai-research", "computer-vision", "ai-tools"], "entities": ["PlaceReasoner-Beta", "PlaceReasoner-Bench", "arXiv", "VLM", "RTL", "EDA", "PPA", "DRC"], "alternates": {"html": "https://wpnews.pro/news/placereasoner-beta-reasoning-driven-macro-placement-and-benchmarking", "markdown": "https://wpnews.pro/news/placereasoner-beta-reasoning-driven-macro-placement-and-benchmarking.md", "text": "https://wpnews.pro/news/placereasoner-beta-reasoning-driven-macro-placement-and-benchmarking.txt", "jsonld": "https://wpnews.pro/news/placereasoner-beta-reasoning-driven-macro-placement-and-benchmarking.jsonld"}}