{"slug": "pcbschemagen-reward-guided-llm-code-synthesis-for-pcb-schematic-design", "title": "PCBSchemaGen: Reward-Guided LLM Code Synthesis for PCB Schematic Design", "summary": "Researchers released PCBSchemaGen_v2, a repository containing two benchmark suites totaling 227 PCB schematic-synthesis tasks and a deterministic 5-layer structural verifier for scoring SKiDL designs against real-IC pin- and topology-level constraints without an LLM, API key, or cached results. The suites comprise PCBBench with 62 hand-authored tasks (17 Easy / 28 Medium / 17 Hard) spanning 41 commercial ICs and Open-Schematics-Eval with 165 tasks (40 Easy / 48 Medium / 77 Hard) spanning 439 commercial ICs, for 480 real ICs across 22 domains. The verifier runs five layers — L1 ERC, L1b Role, L2 Template, L3 Topology, and L4 Power — and is released under the MIT License, with the accompanying paper authored by Huanghaohe Zou, Peng Han, Emad Nazerian, Mafu Zhang, Zhicheng Guo, and Alex Q. Huang for 2026.", "body_md": "This repository provides the **two benchmark suites** and the **deterministic 5-layer verifier** from the paper\n*PCBSchemaGen: Reward-Guided LLM Code Synthesis for Printed Circuit Board (PCB) Schematic Design with Structured Verification*.\n\nIt lets anyone (i) load the **227 PCB schematic-synthesis tasks**, and (ii) run the **deterministic structural verifier**\nthat scores a candidate SKiDL design against real-IC pin- and topology-level constraints — no LLM, no API key,\nand no cached results required.\n\n```\nPCBSchemaGen_v2/\n├── benchmarks/\n│   ├── pcbbench/benchmark.tsv                   # 62 hand-authored tasks (Easy/Medium/Hard)\n│   └── open_schematics/ose_165_task_specs.json  # 165 tasks from public schematics\n├── framework/\n│   ├── topo/                                    # the deterministic 5-layer verifier (self-contained)\n│   └── task_config.yaml                         # per-task verification parameters\n├── kg/kg_open_schematics.json                   # schema-induced KG for Open-Schematics-Eval\n├── component.json / kg_component.json / kg.json # schema-induced KG for PCBBench\n├── requirements.txt\n└── LICENSE\n```\n\n| Suite | Tasks | Difficulty split | Real ICs | Domains | \n|---|---|---|---|---|\n| PCBBench ( `benchmarks/pcbbench/benchmark.tsv` ) | 62 | 17 Easy / 28 Medium / 17 Hard | 41 commercial | 22 | \n| Open-Schematics-Eval ( `benchmarks/open_schematics/ose_165_task_specs.json` ) | 165 | 40 Easy / 48 Medium / 77 Hard | 439 commercial | 22 | \n| **Total** | **227** | 57 / 76 / 94 | 480 | 22 | \n\nEach PCBBench task row specifies: task id, difficulty level, circuit type, the natural-language task, input/output nodes, input/output voltages, and the required-component set.\n\nThe verifier scores a candidate schematic against structural constraints derived from real IC datasheets — fully deterministic, with no golden reference and no functional simulation:\n\n1. **L1 ERC** — electrical invariants (VDD/GND disjointness, power reachability, ground integrity)\n2. **L1b Role** — pin-role compatibility under the 32-role schema\n3. **L2 Template** — per-IC subcategory connection templates\n4. **L3 Topology** — subgraph isomorphism vs. canonical motifs (half-bridge, sync-buck, three-phase inverter, …)\n5. **L4 Power** — domain-specific power rules (Kelvin source, decoupling, isolation, gate-resistor)\n\nSee the paper appendix (verification details) for the full predicate set and reward ladder.\n\n```\npython3 -m pip install -r requirements.txt   # networkx, pyyaml\n```\n\nThe verifier is self-contained in `framework/topo/` (only depends on `networkx`). It exposes, among others:\n\n```\nfrom framework.topo import (\n    KGStore, index_snapshot,\n    check_system_topology, is_complex_task,\n    validate_complex_task, get_validation_feedback_for_llm,\n)\n\n# 1. Load the schema-induced KG (component.json + kg_component.json)\nkg = KGStore(base_dir=\".\")\n\n# 2. Index a candidate design snapshot (nets / parts extracted from a SKiDL build)\nsnapshot = index_snapshot(...)\n\n# 3. Run the layered checks\n#    - system-level validation for Hard / complex tasks:\nreport = validate_complex_task(...)\n#    - or per-layer checks: check_system_topology(...), run_phase2_checks(...)\n```\n\nPer-task verification parameters (match mode, enabled checks, skipped rules) live in\n`framework/task_config.yaml`. Exact function signatures are documented in each module's\ndocstring under `framework/topo/` and in the paper appendix.\n\nReleased under the MIT License (see `LICENSE`). Open-Schematics-Eval tasks are derived from the\npublic `open-schematics` dataset (MIT). Vendor datasheets referenced during KG construction are\ncited, not redistributed.\n\n```\n@inproceedings{pcbschemagen2026,\n  title     = {PCBSchemaGen: Reward-Guided LLM Code Synthesis for Printed Circuit Board (PCB)\n               Schematic Design with Structured Verification},\n  author    = {Zou, Huanghaohe and Han, Peng and Nazerian, Emad and\n               Zhang, Mafu and Guo, Zhicheng and Huang, Alex Q.},\n  year      = {2026},\n}\n```\n\n", "url": "https://wpnews.pro/news/pcbschemagen-reward-guided-llm-code-synthesis-for-pcb-schematic-design", "canonical_source": "https://github.com/HZou9/PCBSchemaGen_v2", "published_at": "2026-09-16 10:48:23+00:00", "updated_at": "2026-09-16 11:13:48.451110+00:00", "lang": "en", "topics": ["ai-research", "large-language-models", "ai-tools", "developer-tools"], "entities": ["PCBSchemaGen", "PCBBench", "Open-Schematics-Eval", "SKiDL", "Huanghaohe Zou", "Peng Han", "Emad Nazerian", "Alex Q. Huang"], "alternates": {"html": "https://wpnews.pro/news/pcbschemagen-reward-guided-llm-code-synthesis-for-pcb-schematic-design", "markdown": "https://wpnews.pro/news/pcbschemagen-reward-guided-llm-code-synthesis-for-pcb-schematic-design.md", "text": "https://wpnews.pro/news/pcbschemagen-reward-guided-llm-code-synthesis-for-pcb-schematic-design.txt", "jsonld": "https://wpnews.pro/news/pcbschemagen-reward-guided-llm-code-synthesis-for-pcb-schematic-design.jsonld"}}