{"slug": "openais-jalapeno-will-be-spicy-but-the-real-sizzle-is-its-chip-design-ai", "title": "OpenAI’s Jalapeño Will Be Spicy, But the Real Sizzle Is Its Chip Design AI", "summary": "OpenAI announced its custom AI inference chip, Jalapeño, designed for large language model inference at gigawatt scale. The chip, built with Broadcom networking and Celestica system integration, aims to deliver superior performance-per-watt for OpenAI's workloads. The move reflects the industry trend of hyperscalers developing proprietary silicon to reduce reliance on single suppliers and optimize hardware-model co-design.", "body_md": "In possibly the worst-kept secret in the industry, OpenAI has been working on its own custom-designed AI inference chip. The chip, named Jalapeño, will be deployed “at Gigawatt scale with data center partners over multiple generations,” according to [a blog posted by the company](https://openai.com/index/openai-broadcom-jalapeno-inference-chip/).\n\nOpenAI said this first-generation accelerator will deliver performance-per-watt “substantially better than current state-of-the-art,” though it did not say whether it is comparing against current-generation GPUs or specially-designed AI accelerator chips. The company already has a deal with Cerebras to use its wafer-scale chips for fast inference at scale, but a number of AI chip companies also claim notable performance-per-watt advantages over GPUs. OpenAI did not say exactly what it expects its power efficiency advantage to be, or over whom.\n\nHyperscalers in the U.S., Europe, and Asia are all working on custom AI chips with varying levels of success so far. The key driver behind these projects is the availability and pricing of the advanced chips needed to run inference workloads at factory scale. Hyperscalers do not like relying on a single company for their compute, and as they scale up, they do not like paying the margins demanded by that company either. Companies in some countries, especially China, have also seen restricted access to chips developed in the U.S. and know that access could be withdrawn at any time.\n\nThe importance of compute to these hyperscalers can’t be overstated—OpenAI president Greg Brockman’s quote in the blog says, “the world is moving to a compute-powered economy,” reflecting the industry’s belief that compute has become a strategic resource to rival electricity, bandwidth, or cloud infrastructure.\n\n[View All](https://www.eetimes.com/category/sponsored-content/)\n\nA much-quoted secondary driver is hardware-model co-design. In theory, since hyperscalers such as OpenAI know their workloads inside and out, and since they, in theory, have good visibility into their own roadmaps, they can design more specialized chips dedicated to their own models. In the OpenAI blog, Richard Ho, the company’s head of hardware, says just this—that the hardware team uses detailed insights from AI researchers.\n\n“We optimized the architecture around the kernels, memory movement, networking, and serving patterns that matter most for frontier AI models,” Ho’s quote in OpenAI’s blog says. “Based on early testing, Jalapeño will efficiently execute our most important workloads close to the hardware’s theoretical limits.”\n\nSilicon-model co-design is certainly a valid goal, but how much advantage it can deliver without specializing to the point of limiting the flexibility to run different current-generation models remains widely debated.\n\nWhat has proven to be critical so far is system design and the orchestration layer: With racks of chips often needed for effective inference, how are those chips and racks joined together? What does the topology look like, what networking chips are used, how many chips are connected, and how big are scale-up domains? OpenAI is using Broadcom Tomahawk networking chips and “connectivity technologies” and working with system integrator Celestica on system design. These parts of the stack are just as critical, if not more so, than the AI accelerator and its local memory at this point.\n\nAs for the chip itself, zooming in on the image provided shows a reticle-sized compute die surrounded by six or eight stacks of high-bandwidth memory. Beyond that, we’ll have to wait for further technology reveal. OpenAI calls Jalapeño an “intelligence processor” and says it will build multiple generations. In a dig at other AI chip companies, the blog says Jalapeño is a “blank slate design for modern LLM inference, not a general-purpose accelerator adapted from earlier AI workloads.” Touché.\n\nSo far, no surprises. Probably the most interesting thing in the announcement is the claim that Jalapeño was developed from initial design to tapeout in nine months—fast by any standards—using OpenAI models for “parts of design and optimization” during the process.\n\nIt makes sense for OpenAI to work on AI for chip design, of course, as a frontier AI lab that wants custom chips. EDA tool vendors are [incorporating advanced AI](https://www.eetimes.com/synopsys-shows-off-first-synopsys-ansys-products/) into all parts of their toolchains, and companies such as [Ricursive](https://www.eetimes.com/startup-ricursive-to-create-an-end-to-end-ai-model-for-chip-design/) and [Cognichip](https://www.eetimes.com/cognichips-artificial-chip-intelligence-will-rely-on-data/) are working on AI for chip design from a clean slate. Several questions remain, however: How far along is OpenAI with automating the chip design process? Is it developing an end-to-end chip design AI within generally intelligent models (like Ricursive) or on a chip-design-specific foundation model (like Cognichip)? Where is it getting its data from? And will it keep this capability for internal use, or will it eventually license the model to EDA vendors, Broadcom, or the broader chip design industry?\n\nOpenAI said it expects initial deployments of Jalapeño to be up and running by the end of the year.\n\n##### See also:\n\n**Startup Ricursive to Create an End-to-End AI Model for Chip Design**\n\nStartup Ricursive, founded by the two leads from Google’s famous AlphaChip project, aims to develop an end-to-end AI model for chip design.", "url": "https://wpnews.pro/news/openais-jalapeno-will-be-spicy-but-the-real-sizzle-is-its-chip-design-ai", "canonical_source": "https://www.eetimes.com/openai-jalapeno-will-be-spicy-but-the-real-sizzle-is-its-chip-design-ai/", "published_at": "2026-06-25 15:59:00+00:00", "updated_at": "2026-06-25 16:20:38.133418+00:00", "lang": "en", "topics": ["ai-chips", "ai-infrastructure", "ai-research", "large-language-models", "ai-products"], "entities": ["OpenAI", "Jalapeño", "Broadcom", "Cerebras", "Celestica", "Greg Brockman", "Richard Ho"], "alternates": {"html": "https://wpnews.pro/news/openais-jalapeno-will-be-spicy-but-the-real-sizzle-is-its-chip-design-ai", "markdown": "https://wpnews.pro/news/openais-jalapeno-will-be-spicy-but-the-real-sizzle-is-its-chip-design-ai.md", "text": "https://wpnews.pro/news/openais-jalapeno-will-be-spicy-but-the-real-sizzle-is-its-chip-design-ai.txt", "jsonld": "https://wpnews.pro/news/openais-jalapeno-will-be-spicy-but-the-real-sizzle-is-its-chip-design-ai.jsonld"}}