Modern chip design is increasingly limited by engineering time. Register transfer level (RTL) development and verification require specialized hardware knowledge, precise reasoning, and repeated interaction with electronic design automation (EDA) tools. LLMs have accelerated code generation, and AI agents extend their impact by using verification feedback to iteratively correct errors.
This is critical for RTL, where correctness depends on precise temporal behavior and many bugs appear only during tool-based validation.
In this post, we discuss how the agentic context evolution (ACE)-RTL agent and NVIDIA Nemotron 3 Ultra work together to deliver leading accuracy and efficiency on agentic RTL tasks. ACE-RTL provides an iterative generate-test-reflect workflow, while Nemotron 3 Ultra contributes long-context reasoning and training aligned with RTL generation, editing, and debugging.
The CVDP benchmark #
The comprehensive Verilog design problems (CVDP) benchmark evaluates LLMs on realistic RTL generation, modification, debugging, and verification tasks. Unlike earlier benchmarks built around short, self-contained Verilog prompts, it better reflects practical hardware design problems.
CID | Category | | cid002 | RTL Code Completion | | cid003 | RTL Natural Language Spec to Code | | cid004 | RTL Code Modification | | cid005 | RTL Spec to RTL with Module Reuse | | cid007 | RTL Code Improvement (Linting/QoR) | | cid012 | Testbench Stimulus Generation | | cid013 | Testbench Checker Generation | | cid014 | Assertion Generation | | cid016 | Debugging / Bug Fixing |
Table 1. CVDP Code Generation Categories
Why RTL coding demands agentic workflows #
RTL coding is not just “write Verilog from a prompt.” A practical assistant must read specifications, understand existing modules, reuse and modify code, interpret simulation failures, debug mismatches, and propose targeted fixes. These are naturally agentic workflows. Engineers rarely solve complex RTL tasks in one attempt; they iterate with compilers, simulators, lint tools, waveform inspection, and verification feedback.
Inside the ACE-RTL agent #
To evaluate Nemotron 3 Ultra in a realistic agentic RTL workflow, we use the ACE-RTL agent from ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs paper. ACE-RTL represents a standard pattern for RTL coding agents: generate RTL, run simulation or tool-based checks, analyze failures, and iteratively refine the design. The agent consists of three cooperating components: a generator, a reflector, and a coordinator. The generator produces or updates RTL code.
The reflector analyzes simulation feedback, identifies likely root causes, and provides high-level fix guidance. The coordinator maintains an evolving debugging context across iterations, deciding which history and feedback should guide the next generation attempt. This allows the agent to build on previous failures instead of repeatedly making similar mistakes.
As shown in Figure 2, above, the ACE-RTL agent substantially improves pass rate across all evaluated models. GLM 5.2 improves from 44.0% as a standalone model to 94.3% with ACE-RTL, Kimi K2.6 improves from 68.6% to 97.1%, and Nemotron 3 Ultra improves from 65.7% to 100.0%. These results highlight the importance of iterative tool feedback and context evolution for solving realistic RTL tasks.
In Figure 3, below, we compare the same ACE-RTL pipeline using GLM 5.2, Kimi K2.6, or Nemotron 3 Ultra as the only LLM in the agent loop. Keeping the agent fixed isolates the effect of the model itself. Across nine CVDP task categories, ACE-RTL with Nemotron 3 Ultra delivers the strongest overall performance, with a 97.1% average pass rate, compared with 95.2% for Kimi K2.6 and 92.1% for GLM 5.2. Its gains are broad across RTL completion, spec-to-RTL generation, RTL modification, module reuse, linting and QoR improvement, testbench stimulus and checker generation, assertion generation, and RTL debugging. Nemotron 3 Ultra also reaches 100% pass rate on several categories.
Importantly, Nemotron 3 Ultra achieves this accuracy with substantially lower token usage. It uses 6,629 tokens per iteration on average, compared with 9,156 for GLM 5.2 and 22,579 for Kimi K2.6. This corresponds to roughly 28% fewer tokens than GLM 5.2 and 71% fewer than Kimi K2.6, while still achieving the highest average pass rate.
This combination of higher accuracy and lower token cost is especially valuable for agentic coding. A higher pass rate means the agent solves more unique hardware problems, while lower token usage reduces inference overhead for each refinement step. In practical terms, that means more RTL tasks can be attempted within the same compute budget, and engineers can get results faster.
Nemotron 3 Ultra is built for long-running agentic reasoning #
Nemotron 3 Ultra is a 550B total-parameter, 55B active-parameter Mixture-of-Experts Hybrid Mamba-Attention model, designed for long-running agents. It was pretrained on 20 trillion text tokens, extended to a 1M-token context length, and among open models in its class, Nemotron 3 Ultra leads on key agentic benchmarks outperforming larger open models despite its smaller footprint.
The hybrid Mamba-Attention architecture improves the throughput efficiency by reducing attention cost and KV-cache footprint, while the MoE design improves accuracy per active parameter, delivering up to 5X higher throughput and 30% lower costs compared to other open models.
For RTL workflows, efficiency matters because the agent context grows quickly. A single debugging iteration may include the specification, module code, generated RTL, simulator output, assertion failures, and prior fix attempts. Efficient long-context inference directly affects whether such agents are practical for real engineers.
Training Nemotron 3 Ultra on the RTL coding tasks #
Nemotron 3 Ultra’s RTL capability benefits from the synthetic data generation (SDG) pipeline proposed in the ACE-RTL paper. The goal of this pipeline is to create high-quality RTL training data that reflects how hardware engineers and RTL agents work in practice: not only generating code from specifications, but also modifying existing implementations and debugging failing designs.
The SDG pipeline starts from high-quality RTL seed designs filtered from public repositories. Open LLMs then convert these seeds into instruction-style training samples, guided by a small set of in-context examples that define the expected format, level of detail, and hardware-specific task style. For spec-to-RTL generation, the LLMs synthesize natural-language specifications paired with golden RTL implementations derived from the seed designs.
The key innovation is task diversity. Beyond spec-to-RTL generation, the pipeline also creates RTL code editing and debugging tasks, which better match how models operate inside an agentic workflow. For editing, the original seed RTL serves as the golden implementation, while a simplified version is used as the input. The paired specification describes the feature extension or corner-case behavior needed to recover the golden RTL.
For debugging, the pipeline injects realistic RTL errors into the seed designs, such as incorrect finite-state-machine transitions, handshake or timing violations, and other common hardware design mistakes. The corresponding specification includes diagnostic information, such as observed failure behavior or signal mismatches, so the model learns to repair faulty RTL using both code context and feedback. All generated samples are passed through a data filter before being used for training. This includes syntax checks, benchmark decontamination, and rubric-based data scoring with an LLM-as-judge to assess whether the specification and RTL implementation are semantically aligned. This filtering step helps ensure that the final synthetic data is both structurally valid and useful for training.
This distinction is critical for agentic RTL workflows. During iterative refinement, the model must reason over previous code, failing tests, and tool feedback, not just generate RTL from a clean specification. By training on code editing and debugging tasks, Nemotron 3 Ultra is exposed to the same types of repair and refinement problems it solves inside an RTL coding agent.
Start building with Nemotron 3 Ultra #
Nemotron 3 Ultra is an open model and can be used today in the tools engineering teams already rely on. Developers can use it to generate RTL and iterate on designs, then plug the output into their existing verification and sign-off flows with partners such as:
Cadence: WhereChipStack AI SuperAgent meets Nemotron 3 Ultra, bringing agentic orchestration to front-end design and verification by coordinating specialized AI agents across RTL generation, testbench creation, regression orchestration, and debugging. Beyond the silicon front-end, Cadence enables Nemotron 3 Ultra open model throughout its portfolio of Super Agents for engineering: InnoStack AI Super Agent for digital implementation and signoff, ViraStack AI Super Agent for custom and analog, and AuraStack AI Super Agent for full multiphysics-driven electronic system design of PCB and Packaging.Siemens: Where Nemotron 3 Ultra pairs with the Questa One Agentic Toolkit to help teams identify issues earlier, improve engineering productivity, and deliver high-quality designs faster. It is also integrated with Fuse EDA AI Agent for powering long-running, self-verifying EDA AI agents at up to 5x to 10x higher token efficiency.- Synopsys AgentEngineer: Where technology, leveraging Nemotron 3 Ultra models, achieves autonomous verification closure with a multi-agent system that enables a continuous, traceable feedback loop, significantly reducing manual verification effort. Its Openshell Sandbox can reduce weeks of manual verification effort to hours.
Going further #
Stay up to date on* NVIDIA Nemotron** by subscribing to NVIDIA news and following NVIDIA AI on LinkedIn, X, Discord, and YouTube.*
Visit the Nemotron developer page for resources to get started. Explore open Nemotron models and datasets on Hugging Face and Blueprints on build.nvidia.com .
Engage with Nemotron livestreams, tutorials, and the developer community on the NVIDIA forum and the Nemotron channel on Discord.