NVIDIA and Cisco USFP Optics Target 400Gb/s per Lane, With MGX 1.2 and DSX OS Updates at OCP 2026

NVIDIA and Cisco announced plans for Ultra-Dense Small Form Factor Pluggable (USFP), an optical module format targeting 400Gb/s per lane in AI fabrics, with first planned transceivers packing 16 full-duplex lanes into an OSFP-sized footprint for 6.4Tb/s per module and a connector designed to scale to 32 lanes and 12.8Tb/s. The companies claim USFP delivers 4x the bandwidth and front-panel density of 200Gb/s-per-lane pluggables at about 1.3x the power efficiency, and they intend to turn the design into an open industry specification through a community-led multi-source agreement, though no sampling schedule or availability date was given. NVIDIA also contributed its Vera Rubin rack and compute tray designs to OCP through the third-generation MGX 1.2 reference design, which adds rack-scale blind-mate liquid cooling, interoperable rack-scale interconnect infrastructure, and a liquid-cooled 5,000A busbar with support for rack deployments up to 250kW.

NVIDIA and Cisco announced plans today for Ultra-Dense Small Form Factor Pluggable USFP , an optical module format built for 400Gb/s-per-lane Ethernet in AI fabrics. The first planned transceivers put 16 full-duplex lanes in a footprint about the size of an OSFP module, which works out to 6.4Tb/s per module, and the connector is designed to grow to 32 lanes and 12.8Tb/s. NVIDIA and Cisco say USFP delivers 4x the bandwidth and front-panel density of 200Gb/s-per-lane pluggables at about 1.3x the power efficiency. USFP is a plan with no sampling schedule or availability date, and NVIDIA and Cisco intend to turn the design into an open industry specification through a community-led multi-source agreement. It is one piece of a larger set of NVIDIA contributions at the OCP Global Summit that also covers Vera Rubin rack designs, DSX AI factory software, facility and grid specifications, 800 VDC power, and Ethernet work with Meta and Google. USFP Increases Lane Count and Front-Panel Bandwidth Density USFP doubles both the lane count and the per-lane rate of today’s modules, which NVIDIA and Cisco say lets a switch connect more 1.6Tb/s endpoints without adding a network tier. The modules are meant for switches and SuperNICs alike. The companies treat front-panel density as the limiting factor in AI fabric growth: once a switch runs out of ports, the next step is another switch layer with more optics, which adds latency, power, and cost. USFP keeps the pluggable model, so modules stay field-replaceable and serviceable. “Building the world’s largest AI factories starts with rethinking the smallest of connections,” said Gilad Shainer, senior vice president at NVIDIA. Bill Gartner, senior vice president and general manager of optical systems and optics at Cisco, said that pushing pluggable optics to 400Gb/s per lane needed more than an incremental extension of current module designs. A New Connector Supports 400Gb/s Signaling The connector is a two-dimensional contact array with a two-step insertion sequence, in which the high-speed contacts engage only after the module is seated. NVIDIA and Cisco say that reduces contact wear, improves signal integrity, and makes insertion force more predictable. The connector is designed for 400Gb/s per lane and, according to the companies, also improves performance at 200Gb/s per lane. A USFP module can dissipate up to 100W without a dedicated cooling circuit inside the transceiver, which the companies say simplifies switch design and improves reliability. Every USFP configuration supports optical designs that simplify signal processing to cut latency and power, and the format accommodates a range of optical technologies and reach classes. NVIDIA and Cisco are working with TE Connectivity and Amphenol on cages, connectors, and modules, with more partners expected, building on their existing interoperability work between NVIDIA Spectrum-X and Cisco Silicon One-based Ethernet networks. MGX 1.2 Extends Vera Rubin Rack Infrastructure NVIDIA contributed its Vera Rubin https://www.storagereview.com/news/nvidia-launches-vera-rubin-architecture-at-ces-2026-the-vr-nvl72-rack rack and compute tray designs to OCP through its open MGX architecture, as part of the third-generation MGX reference design in OCP’s Open DC Initiative, alongside the MQD and MQDB open liquid-cooling designs. The MGX 1.2 specification adds rack-scale blind-mate liquid cooling, interoperable rack-scale interconnect infrastructure, and a liquid-cooled 5,000A busbar, with native support for 19-inch equipment and rack deployments up to 250kW. Configurable I/O bays, fanless liquid-cooled compute trays, and standardized power and cooling interfaces round out the specification, and NVIDIA says the common interfaces shorten assembly, test, and service times for partners. A separate Vera CPU https://www.storagereview.com/news/coreweave-vera-rubin-nvl72-production-cognition-4-8x-vera-cpu-forge rack design specification extends MGX beyond accelerated computing. NVIDIA positions Vera Rubin NVL72 as the platform for large-scale training and inference, and the Vera CPU rack for the tool calling, orchestration, and sandboxed execution that agentic workloads add. DSX OS Adds Network, Rack and Cluster Management Components NVIDIA expanded DSX OS, the open operating layer of its DSX https://www.storagereview.com/news/nvidia-dsx-ready-qualifies-tesla-lg-and-hitachi-batteries-and-vertiv-liquidstack-and-lg-cdus-for-ai-factories AI factory platform, with four open-source components. NVIDIA Config Manager automates switch configuration, validation, and maintenance across AI fabrics. NVIDIA Cluster Readiness Engine stress-tests GPU clusters with workload simulations before training starts, which NVIDIA says catches hardware problems that would otherwise fail jobs. NVIDIA Rack Management Service treats the rack as the unit of operation, with hardware abstraction and firmware management at that level. Cluster API Provider for NVIDIA Infrastructure Controller handles bare-metal deployment and tenant onboarding, and NVIDIA claims it turns raw hardware into production-ready clusters in hours. The components come out of NVIDIA’s experience running DGX Cloud, and they are meant to let cloud providers and software partners fold AI factory operations into multi-tenant platforms. Open Specifications Cover Facility Design and Grid Recovery NVIDIA, AMD, Google, and Meta published Open Data Center Specification v0.7, a shared facility blueprint covering power architecture, cooling, and physical layout that equipment makers, colocation providers, and operators can design against. Google, Meta, Microsoft, and NVIDIA also published the OCP Grid Resilience Specification, which defines how large AI facilities should ride through utility disturbances: stay connected, respond automatically, and return to near-full load in under two seconds. NVIDIA says both specifications line up with its DSX reference design. Visionbay introduced plans for K-1, an AI factory platform that pairs NVIDIA’s 800 VDC https://www.storagereview.com/news/nvidia-moves-800-vdc-power-architecture-from-concept-to-production-just-dont-turn-off-ac-power-yet reference architecture with Vertiv power and thermal equipment for future Vera Rubin deployments. K-1 moves AC-to-DC conversion into cluster-level power centers and distributes 800 VDC closer to the compute, with phased adoption of 800 VDC, liquid cooling, and modular expansion, and Visionbay has not given a deployment date. Meta Adopts Spectrum-6 and Multiplane Networking Meta will adopt NVIDIA Spectrum-6 https://www.storagereview.com/news/nvidia-gtc-2026-rubin-gpus-groq-lpus-vera-cpus-and-what-nvidia-is-building-for-trillion-parameter-inference 102.4Tb/s Ethernet for its Vera Rubin AI factories. NVIDIA says Spectrum-6 doubles the switching capacity and per-lane bandwidth of Spectrum-4, running at 200G per lane with performance isolation between jobs. Meta’s Spectrum-6-based N-IceCube switch goes into its IcePack 100T liquid-cooled rack and runs FBOSS, Meta’s open switch software, which uses the OCP Switch Abstraction Interface for vendor-independent control of the hardware. Spectrum-X Multiplane pairs Spectrum-6 switches with ConnectX-9 SuperNICs and spreads GPU traffic in hardware across up to eight independent network planes. NVIDIA says the design scales past 100,000 GPUs with fewer switch tiers, and when a component fails, traffic shifts to the remaining planes so jobs continue at reduced bandwidth. Meta and NVIDIA say they have validated the resilience gains on premises and in the cloud, without publishing figures. Google Falcon Transport Targets Future NVIDIA Networking Hardware NVIDIA and Google announced Falcon Transport support for future NVIDIA ConnectX-10 SuperNICs and BlueField DPUs. Falcon delivers reliable data over Ethernet through multipath load balancing, programmable congestion control, hardware-based loss recovery, and per-connection security. NVIDIA implements it with hardware acceleration and DOCA software, so NVIDIA and Google NICs speak a common transport while applications keep standard RDMA interfaces. The companies say that improves bandwidth utilization and performance predictability for AI and storage traffic as Ethernet fabrics scale.