{"slug": "nvidia-accelerates-chip-engineering-with-ai-agents", "title": "Nvidia Accelerates Chip Engineering With AI Agents", "summary": "Nvidia is deploying AI agents and its new Arm-based Vera CV100 CPU to accelerate chip engineering, as traditional design processes can no longer keep pace with the complexity of modern semiconductors. Tim Costa, vice president and general manager of computational engineering at Nvidia, said the industry will need to produce 2 trillion chips and process 41 million wafers per month by 2030, with individual packages approaching a trillion transistors. Nvidia is expanding its Agent Toolkit with updated CUDA-X and PhysicsNeMo libraries and working with Cadence and Synopsys to use Vera for simulation, verification, and implementation, achieving 1.5 times the performance of AMD's Epyc Torrent systems in early tests.", "body_md": "# Nvidia Accelerates Chip Engineering With AI Agents\n\nMore than a decade ago, Nvidia turned its full focus on artificial intelligence, and since then has been [churning out GPUs](https://www.nextplatform.com/compute/2026/06/30/three-hpc-gurus-ask-do-we-still-need-gpus/5264552) – [and now CPUs](https://www.nextplatform.com/compute/2026/03/19/driving-down-the-ai-system-roadmap-with-nvidia/5210195) – and other hardware designed to power AI systems as well as a wealth of software libraries through CUDA-X and a family of AI models with under the Nemotron umbrella. This has put Nvidia in a leadership role in a rapidly expanding AI industry that has taken over enterprise and HPC datacenter development and made the company extraordinarily wealthy.\n\nPart of what drives that wealth is the fact that silicon engineering for AI is increasingly complex with every generation, with demand not only for more chips but also more capabilities, a situation that is pushing the industry beyond what traditional methods can handle. Tim Costa, vice president and general manager of computational engineering at Nvidia, put it in terms that go beyond simply scaling to meet demand.\n\nSpeaking with journalists in a video call, Costa noted that by 2030 the industry is expected to produce 2 trillion chips and process about 41 million wafers a month. In addition, individual packages are approaching a trillion transistors while entire computing systems are on their way to transistor counts that will reach into the quadrillions. At the same time, bringing a chip to market can take years as engineers spend years on the simulation, verification, and implementation steps. That’s a lifetime in the accelerated age of AI.\n\n### Complexity Outpaces Tradition Chip Design\n\n“The key point is not any one number; it's the interaction of scale, architecture, packaging, and system complexity,” he said. “The traditional design process just can't keep pace with that scale of challenge. To meet it, AI and accelerated computing are moving from productivity tools into being foundational engineering infrastructure.”\n\nThis is where Nvidia and other chip engineering firms are turning to AI.\n\n“This complexity is compounded by the coupled end-to-end nature of semiconductor innovation,” Costa said. “Decisions in chip architecture affect atomic-scale manufacturing, advanced packaging power, thermals, and the behavior of the complete system. AI helps engineers explore far more design alternatives and make better decisions across those interactions. Accelerated computing makes the high-fidelity simulation, validation, and optimization behind those decisions fast enough to repeat.”\n\nRather than replacing physics or design rules, bringing AI into the chip development process lets engineers put such checks into the loop and use them more often, he explained, adding “the opportunity is to accelerate the full engineering loop, not isolated tools.”\n\nNvidia also is expanding its Agent Toolkit to include updated CUDA-X and PhysicsNeMo libraries for training and deploying engineering AI.\n\nIn addition, the vendor is working with chip engineering firms Cadence and Synopsys in using its Arm-based “Vera” CV100 CPU (below) to accelerate future generations of its CPUs and GPUs.\n\nVera holds 88 custom “Olympus” CPU cores designed by Nvidia and a 1.2 TB/sec LPDDR5X memory subsystem. The company’s second-generation Scalable Coherency Fabric mesh interconnect for strong per-core performance, high memory bandwidth, and low latency for engineering applications, according to Nvidia.\n\n“Nvidia is deploying Vera across the EDA [electronic design automation] workflows used to create our future CPUs and GPUs, including simulation, formal verification, and physical implementation,” Costa said, noting that early engineering testing shows Vera running on Synopsys’ VCS and Cadence’s Jasper platforms provide 1.5 times the performance of AMD’s Epyc Torrent systems. “Its practical value is shorter simulation verification runs. Engineering teams can iterate faster. We are working with Cadence and Synopsys to optimize leading EVA applications for Vera by putting Vera to work helping design Rosa.”\n\n“[Rosa,” of course, is Nvidia’s next-generation CPU](https://www.nextplatform.com/compute/2026/03/19/driving-down-the-ai-system-roadmap-with-nvidia/5210195) built on its Rigel core. It is due to launch in 2028 as part of the vendor’s upcoming Feynman datacenter platform.\n\nBoth Cadence and Synopsys are [going hard into using agentic AI](https://www.nextplatform.com/ai/2026/04/16/the-embrace-of-ai-in-design-transforms-cadence-and-its-customers/5217962) for their EDA and other chip design capabilities. Cadence in February announced AI Super Agent, an agentic tool for silicon design and verification, and in the following two months unveiled partnerships with Nvidia, TSMC, and Google around using AI agents for chip and system designs. Last month came the launch of AuraStack AI Super Agent (below) for front-end agentic workflow for automated chip design and verification.\n\nThe AI Super Agents, at the direction of engineers, can simultaneously implement hundreds of simulation to do in less than a day work that now requires five weeks, providing [40-times faster Register-Transfer Level (RTL) validation cycles](https://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/the-autonomous-chip-to-system-engineer-has-arrived), according to Cadence.\n\nFor its part, Synopsys not only is partnering with Nvidia, but this week announced similar agentic AI-based collaborations with [AMD, Microsoft](https://news.synopsys.com/2026-07-27-Synopsys-Advances-Agentic-AI-Chip-Design-with-AMD-and-Microsoft), and [Intel](https://news.synopsys.com/2026-07-27-Synopsys-and-Intel-Foundry-Fast-Track-Customer-Readiness-from-Silicon-to-Systems-on-Intel-14A). At the Design Automation Conference this week in California, Synopsys demonstrated its [Fully Autonomous Design Verification Workflow](https://news.synopsys.com/2026-07-26-Synopsys-Showcases-Comprehensive-Autonomous-Engineering-Workflows-from-Silicon-to-Systems,-Developed-with-NVIDIA-Technology) (below) that is based on its agentic platform and AgentEngineer technology and includes Nvidia technologies, such as its new Nemotron 3 Ultra model, Agent Toolkit, and OpenShell runtime. The vendor said it can deliver validated RTL 50 times faster than other platforms.\n\nNvidia in March [launched its Agent Toolkit](https://www.nextplatform.com/code/2026/03/18/the-open-agentic-ai-world-according-to-nvidia/5209529), with core components including the Nemotron models and OpenShell runtime and a month ago unveiled Nemotron 3 Ultra, an open model for agentic coding for chip designs. Now the vendor is expanding the toolkit, including with a rearchitected PhysicsNeMo so agents can train and deploy AI physics models for design and simulation work.\n\n“PhysicsNeMmo began as a framework that helped specialists build, train, and deploy AI models for AI physics,” Costa said. “We are now organizing that expertise as a collection of open, composable libraries with agent-ready skills. The libraries cover the practical layers and engineering workflow needs, physics-aware operations, GPU-native mesh processing, distributed training, and data curation, the skills that encode repeatable instructions for tasks such as model acceleration, configuring a training recipe, creating a data pipeline, or curating a data set, including which tools to call, what outputs to produce, and how the results should be checked.”\n\nHe added that “the shift is from a framework an expert operates manually to AI physics capabilities an agent can invoke, compose, and validate inside a larger engineering process.”\n\nCUDA-X has included acceleration libraries for direct sparse solvers in cuDSS for large and complex sparse linear systems that are key to EDA and scientific simulation, as well as cuEST for quantum chemistry simulations to scales that meet the need of devices. It now includes cuISS for large sparse linear systems for physics and engineering simulations on GPUs.\n\n“Many engineering applications begin with partial differential equations,” Costa said. “Once those equations are discretized – or made discrete-ready to compute on a computer – the workload often becomes a very large sparse linear system. Direct solvers remain essential ... but many applications in engineering require iterative methods for memory efficiency and scalability. cuISS brings GPU-native iterative sparse solvers and preconditioning building blocks into CUDA-X.”", "url": "https://wpnews.pro/news/nvidia-accelerates-chip-engineering-with-ai-agents", "canonical_source": "https://www.nextplatform.com/hpc/2026/07/27/nvidia-accelerates-chip-engineering-with-ai-agents/5279125", "published_at": "2026-07-27 18:04:01+00:00", "updated_at": "2026-07-27 18:24:09.626276+00:00", "lang": "en", "topics": ["artificial-intelligence", "ai-agents", "ai-infrastructure", "ai-chips", "ai-tools"], "entities": ["Nvidia", "Tim Costa", "Cadence", "Synopsys", "Vera CV100 CPU", "CUDA-X", "PhysicsNeMo", "AMD Epyc Torrent"], "alternates": {"html": "https://wpnews.pro/news/nvidia-accelerates-chip-engineering-with-ai-agents", "markdown": "https://wpnews.pro/news/nvidia-accelerates-chip-engineering-with-ai-agents.md", "text": "https://wpnews.pro/news/nvidia-accelerates-chip-engineering-with-ai-agents.txt", "jsonld": "https://wpnews.pro/news/nvidia-accelerates-chip-engineering-with-ai-agents.jsonld"}}