{"slug": "memristive-singular-value-decomposition", "title": "Memristive Singular Value Decomposition", "summary": "Researchers presented memristive SVD (MSVD), a singular value decomposition system built on compute-in-memory memristor chips and enabled by a selective representation enhanced architecture (SREA), reporting order-of-magnitude gains in energy efficiency and speed over conventional hardware across three demonstrated scenarios. The system was demonstrated on low-rank approximation for image enhancement and epidemiological data reconstruction, user-scalable recognition using persistent in-memory storage, and large language model weight decomposition, where MSVD-based initialization consistently outperformed standard fine-tuning on mathematical benchmarks. SREA also reduced energy overhead and accelerated convergence over unenhanced MSVD, with the advantages growing with each update cycle in the incremental setting.", "body_md": "## Abstract\n\nSingular value decomposition (SVD) underpins low-rank representation across scientific computing, signal processing, and machine learning. However, iterative computations in SVD are energy-intensive on conventional von Neumann architectures with separate storage and computation units, posing significant challenges for complex information processing. Here, we present memristive SVD (MSVD), built on compute-in-memory (CIM) memristor chips, enabled by a selective representation enhanced architecture (SREA) that ensures numerical fidelity across iterations. We demonstrate MSVD across three tiers of increasing complexity: low-rank approximation for image enhancement and epidemiological data reconstruction; user-scalable recognition where incremental MSVD exploits persistent in-memory storage to incorporate new users without remapping existing information; and large language model weight decomposition where MSVD-based initialization consistently outperforms the standard fine-tuning method on mathematical benchmarks. Beyond software-comparable accuracy, SREA reduces energy overhead and accelerates convergence over unenhanced MSVD, and the full system achieves order-of-magnitude gains in energy efficiency and speed over conventional hardware across all demonstrated scenarios, with these advantages growing progressively with each update cycle in the incremental setting. This work accelerates SVD across various scenarios and extends memristor-based systems towards general computing applications.\n\n### Similar content being viewed by others\n\n## Introduction\n\nLow-rank representations extract essential patterns from high-dimensional datasets while substantially reducing computational complexity, serving as a critical tool across diverse applications, from life sciences<sup>[1](#ref-CR1),[2](#ref-CR2),[3](#ref-CR3),[4](#ref-CR4),[5](https://www.nature.com/articles/s41467-026-76272-2#ref-CR5)</sup> to information engineering<sup>[6](#ref-CR6),[7](#ref-CR7),[8](#ref-CR8),[9](#ref-CR9),[10](#ref-CR10),[11](#ref-CR11),[12](#ref-CR12),[13](#ref-CR13),[14](https://www.nature.com/articles/s41467-026-76272-2#ref-CR14)</sup>. As data processing increasingly shifts from centralized cloud computing to distributed edge devices, resource limitations necessitate highly efficient on-device analysis. Singular value decomposition (SVD) provides the mathematically optimal low-rank approximation with guaranteed minimal information loss, positioning it as the preferred method for such environments. Recently, SVD-based biomedical information processing<sup>[1](https://www.nature.com/articles/s41467-026-76272-2#ref-CR1),[4](https://www.nature.com/articles/s41467-026-76272-2#ref-CR4)</sup> and large language model (LLM) adaptation<sup>[15](https://www.nature.com/articles/s41467-026-76272-2#ref-CR15),[16](https://www.nature.com/articles/s41467-026-76272-2#ref-CR16)</sup> have attracted great attention. However, SVD typically relies on complex iteration-deflation approaches featuring intensive iterative vector-matrix multiplications<sup>[17](https://www.nature.com/articles/s41467-026-76272-2#ref-CR17),[18](https://www.nature.com/articles/s41467-026-76272-2#ref-CR18)</sup>. When implemented on conventional complementary metal-oxide semiconductor (CMOS)-based von Neumann architectures, these computations result in high energy consumption and long processing times due to frequent data movement during the iterative process, problems that worsen as data volumes grow<sup>[19](#ref-CR19),[20](#ref-CR20),[21](#ref-CR21),[22](#ref-CR22),[23](https://www.nature.com/articles/s41467-026-76272-2#ref-CR23)</sup>. Moreover, as Moore’s law approaches its physical limits<sup>[24](https://www.nature.com/articles/s41467-026-76272-2#ref-CR24)</sup>, further reducing the energy consumption per iteration in traditional hardware becomes increasingly challenging, limiting the scalability of SVD computations<sup>[20](https://www.nature.com/articles/s41467-026-76272-2#ref-CR20),[25](https://www.nature.com/articles/s41467-026-76272-2#ref-CR25)</sup>. In contrast, memristor-based compute-in-memory (CIM) offers a promising solution for efficient SVD computations. By merging storage and computation and exploiting Ohm’s and Kirchhoff’s laws for in situ computation<sup>[26](#ref-CR26),[27](#ref-CR27),[28](https://www.nature.com/articles/s41467-026-76272-2#ref-CR28)</sup>, this approach promises dramatically reduced energy consumption and enhanced processing speeds.\n\nBuilding upon these inherent advantages, memristor-based computing has shown promising results in various domains. Recent studies have actively explored memristor-based CIM implementations for accelerating deep learning tasks<sup>[29](#ref-CR29),[30](#ref-CR30),[31](#ref-CR31),[32](#ref-CR32),[33](#ref-CR33),[34](#ref-CR34),[35](#ref-CR35),[36](#ref-CR36),[37](https://www.nature.com/articles/s41467-026-76272-2#ref-CR37)</sup>. Furthermore, growing research has confirmed the feasibility of memristor-based CIM in accelerating scientific computing tasks<sup>[38](#ref-CR38),[39](#ref-CR39),[40](#ref-CR40),[41](#ref-CR41),[42](#ref-CR42),[43](https://www.nature.com/articles/s41467-026-76272-2#ref-CR43)</sup>, such as solving linear equations<sup>[38](https://www.nature.com/articles/s41467-026-76272-2#ref-CR38),[39](https://www.nature.com/articles/s41467-026-76272-2#ref-CR39)</sup>, partial differential equations<sup>[40](#ref-CR40),[41](#ref-CR41),[42](#ref-CR42),[43](https://www.nature.com/articles/s41467-026-76272-2#ref-CR43)</sup> and matrix inversion<sup>[39](https://www.nature.com/articles/s41467-026-76272-2#ref-CR39)</sup>. While these applications typically rely on relatively straightforward iterative processes<sup>[39](#ref-CR39),[40](#ref-CR40),[41](#ref-CR41),[42](https://www.nature.com/articles/s41467-026-76272-2#ref-CR42),[44](https://www.nature.com/articles/s41467-026-76272-2#ref-CR44),[45](https://www.nature.com/articles/s41467-026-76272-2#ref-CR45)</sup>, SVD using the power iteration-deflation approach involves a unique dual-matrix iteration process, producing multi-scale outputs sequentially from high to low significance (Supplementary Fig. [1](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). When implementing memristive SVD (MSVD, Fig. [1](https://www.nature.com/articles/s41467-026-76272-2#Fig1)), these unique characteristics, combined with inherent hardware constraints, lead to two critical computational challenges: Firstly, numerical drift occurs during the iteration stage when calculating the largest singular value and corresponding singular vectors. This drift results from accumulated computational inaccuracies caused by memristor conductance fluctuations as iterations progress. Secondly, residual components emerge during the deflation stage when removing the influence of the calculated singular value from the original matrix to identify the next largest singular value. These residuals arise from mapping deviations in updated singular vectors stored in memristors. Existing precision improvement techniques<sup>[40](https://www.nature.com/articles/s41467-026-76272-2#ref-CR40),[46](#ref-CR46),[47](#ref-CR47),[48](#ref-CR48),[49](#ref-CR49),[50](#ref-CR50),[51](https://www.nature.com/articles/s41467-026-76272-2#ref-CR51)</sup> have shown effectiveness in conventional tasks (Supplementary Table [1](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). However, the unique challenges arising from dual-matrix iteration and multi-scale output in SVD computation remain insufficiently addressed, presenting a significant barrier to MSVD.\n\nIn this work, we introduce a selective representation enhanced architecture (SREA) to bridge the gap between the SVD algorithm and CIM hardware for high-fidelity MSVD. Our SREA incorporates dual-precision mapping (DPM) to reduce numerical drift and vector processing refinement (VPR) to minimize deflation residuals. We evaluated the MSVD with SREA across diverse applications with varying matrix dimensions and properties, demonstrating its versatility, scalability and superiority. In an image enhancement task, our approach achieved a 31.0 dB peak signal-to-noise ratio (PSNR) and 0.940 structural similarity index measure (SSIM) compared to software-based results. For temporal data analysis, the MSVD exhibited excellent performance, attaining a correlation coefficient of 0.999 in reconstructing hospital admission data during the COVID-19 pandemic<sup>[52](https://www.nature.com/articles/s41467-026-76272-2#ref-CR52)</sup>. For edge learning applications, we developed an incremental MSVD method for user-scalable gesture recognition and sleep stage detection using biomedical signals. The incremental approach maintained robust performance, surpassing non-incremental approaches by 19.29% and 11.07% in accuracy across these two tasks, respectively. Furthermore, we validated the potential of MSVD in larger-scale applications through LLM tuning with MSVD-based initialization. Specifically, for the LLaMA 3.2-3B model, the MSVD-based method outperformed the standard fine-tuning method by 4.85 points (a 10.45% relative improvement) on the GSM8K<sup>[53](https://www.nature.com/articles/s41467-026-76272-2#ref-CR53)</sup> dataset and 0.68 points (a 6.27% relative improvement) on the MATH<sup>[54](https://www.nature.com/articles/s41467-026-76272-2#ref-CR54)</sup> dataset.\n\nBeyond achieving high accuracy across applications, performance benchmarks demonstrate the significant efficiency advantages of our approach. Through an optimized convergence process, SREA reduces energy consumption by 48.5% and improves speed by 48.1% compared to MSVD without SREA, achieving 29.9× higher energy efficiency and 19.0× faster normalized speed compared to conventional CMOS hardware. The incremental MSVD approach scales effectively, delivering 67.1× higher energy efficiency and 39.7× faster normalized speed compared to conventional CMOS-based computation. Additionally, for LLaMA 3.2-3B model initialization, MSVD achieves 41.6× higher energy efficiency and 23.1× faster speed compared to CMOS-based hardware.\n\n## Results\n\n### Design of memristive singular value decomposition\n\nSVD decomposes the data matrix ${{{\\boldsymbol{X}}}}$ into three matrices: ${{{\\boldsymbol{U}}}}$, formed by left singular vectors (LSVs); ${{{\\boldsymbol{S}}}}$, holding the singular values; and ${{{\\boldsymbol{V}}}}$, containing the right singular vectors (RSVs). MSVD employs a power iteration-deflation approach to sequentially extract these components. As illustrated in Fig. [2a](https://www.nature.com/articles/s41467-026-76272-2#Fig2), the computation for each singular vector is executed through an iterative loop (marked in blue). Starting with a randomly initialized input voltage vector ($\\widetilde{{{{\\boldsymbol{v}}}}}$), the process performs dual matrix multiplications on two memristor subarrays: one storing the data matrix (${{{\\boldsymbol{X}}}}$) and the other storing the previously solved RSVs (${{{\\boldsymbol{V}}}}$). The multiplication on the data matrix executes one step of power iteration, while the multiplications on previously solved RSVs calculates the components to be deflated. The multiplication output from RSVs is then subtracted from the output of the data matrix to update $\\widetilde{{{{\\boldsymbol{v}}}}}$, effectively completing the deflation to isolate the target singular vector. These operations form one iteration step of the loop. Once the loop converges or stops, the newly solved RSV (${{{\\boldsymbol{v}}}}$, obtained from converged $\\widetilde{{{{\\boldsymbol{v}}}}}$) is updated into ${{{\\boldsymbol{V}}}}$ for subsequent power iteration and deflation steps (illustrated in red loop in Fig. [2a](https://www.nature.com/articles/s41467-026-76272-2#Fig2)). The corresponding singular value ($s$) and LSV (${{{\\boldsymbol{u}}}}$) are then derived through multiplications involving the newly solved RSV and the data matrix. By repeating this process, we can calculate the complete matrices ${{{\\boldsymbol{U}}}}$, ${{{\\boldsymbol{S}}}}$, and ${{{\\boldsymbol{V}}}}$. See **Methods** for details.\n\nHowever, mapping deviations and reading fluctuations in memristors<sup>[41](https://www.nature.com/articles/s41467-026-76272-2#ref-CR41),[46](https://www.nature.com/articles/s41467-026-76272-2#ref-CR46),[55](https://www.nature.com/articles/s41467-026-76272-2#ref-CR55)</sup> can significantly degrade MSVD computational accuracy. During power iteration, limited representation precision and reading fluctuations in the memristor-based data matrix cause numerical drifting (Fig. [2b](https://www.nature.com/articles/s41467-026-76272-2#Fig2)), leading to convergence instability and imprecise outputs. During deflation, as the inputs to the RSVs are scaled by the square of solved singular values, the inaccuracies in input representation and errors from mapping deviations of in-memory RSVs result in residuals of the component that fails to be deflated (Fig. [2c](https://www.nature.com/articles/s41467-026-76272-2#Fig2)). Substantial residuals can influence or even replace subsequent target singular vectors and values. Consequently, the direct implementation of the SVD on memristor arrays is impractical.\n\nTo address these challenges and enable high-fidelity MSVD, we propose SREA (Fig. [2d](https://www.nature.com/articles/s41467-026-76272-2#Fig2)), incorporating dual-precision mapping and vector processing refinement (DPM and VPR, see details in **Methods**). DPM partitions the matrices into high-order and low-order components (e.g., mapping an 8-bit matrix onto a low-resolution array storing the 2 high-order bits and a high-resolution array storing the 6 low-order bits). By allocating the high-order part to low-resolution memristor states, DPM ensures the physical robustness of critical bits, preventing deviations of the high-order part from being amplified by their large positional weights. Concurrently, mapping the low-order part to high-resolution states preserves fine-grained numerical precision. This mapping strategy mitigates numerical drift and provides a robust foundation for precise iterations. Complementarily, VPR mitigates the error amplification during deflation. Since RSV inputs possess a large dynamic range as scaled by square of singular values, VPR assigns higher precision to these specific inputs (e.g., applying 12-bit precision to these inputs within a standard 8-bit system precision) to prevent quantization errors from being amplified in subsequent multiplications. To counter memristor variations, each solved RSV is replicated several times within the crossbar array, with the replicas’ outputs summed at the output line and then averaged. Together, VPR effectively reduces the residual components.\n\nWhile generic bit-slicing techniques have been developed for memristor-based vector-matrix multiplications<sup>[51](https://www.nature.com/articles/s41467-026-76272-2#ref-CR51)</sup>, MSVD requires specialized precision management. DPM utilizes a high-order-error-aware strategy to mitigate the error amplification commonly observed in uniform positional bit-slicing, without introducing excessive overhead. Concurrently, VPR precisely addresses the expanded input dynamic range and the consequently magnified errors from memristor variations specific to RSVs, rather than relying on global equal-fill bit-slicing. Ultimately, by elevating the optimization focus to the system-level iterative task of MSVD, SREA achieves a precision-cost balance (Supplementary Table [2](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)), making efficient MSVD practically viable.\n\nTo validate our approach, we experimentally demonstrate MSVD on our customized memristor hardware platform<sup>[56](https://www.nature.com/articles/s41467-026-76272-2#ref-CR56)</sup> (**Methods** and Supplementary Fig. [2](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)), which consists of a 130 nm memristor chip (Fig. [2e](https://www.nature.com/articles/s41467-026-76272-2#Fig2), and Supplementary Fig. [3](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). This chip contains a memristor array and peripheral circuits for efficient mapping, reading, and parallel computing. The memristors feature a TiN/TaO<sub>x</sub>/HfO<sub>2</sub>/TiN stack with HfO<sub>2</sub> as the resistive switching layer and TaO<sub>x</sub> as a thermal enhancement layer for improved analog switching (Supplementary Fig. [4a, b](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). Continuous conductance modulation through SET and RESET operations enables high precision mapping of matrix entries onto memristor conductance (Fig. [2f](https://www.nature.com/articles/s41467-026-76272-2#Fig2), and Supplementary Fig. [5](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). The measurement of device mapping deviation and reading fluctuation quantifies the hardware non-idealities that compromise accuracy (Fig. [2g](https://www.nature.com/articles/s41467-026-76272-2#Fig2), and Supplementary Fig. [4c](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)), underscoring the necessity of SREA design. Constrained by limited memristor array size, large-scale evaluations were conducted using hardware-calibrated simulations. This simulation framework incorporates a noise model calibrated from actual memristor measurements and the functions of peripheral circuits. See **Methods** and Supplementary Table [3](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) for more details on the system and experiment configurations.\n\n### Convergence characterization\n\nTo validate the effectiveness of SREA, we first conducted experiments on the IRIS dataset<sup>[57](https://www.nature.com/articles/s41467-026-76272-2#ref-CR57)</sup> (150 × 4 matrix). SREA was configured with a [2, 5] bit slicing for DPM; 6 additional input bits (with a system standard 8-bit input precision), and 4-times vector repetition for VPR. Figure [3a](https://www.nature.com/articles/s41467-026-76272-2#Fig3) shows singular values calculated by MSVD with and without SREA, averaged over 20 experiments. The first singular value converges quickly, while subsequent values converge more slowly due to accumulated residuals. MSVD with SREA yields smaller errors, indicating faster and more accurate iterations. Figure [3b](https://www.nature.com/articles/s41467-026-76272-2#Fig3) compares the normalized errors of singular values computed by MSVD with and without SREA. MSVD with SREA demonstrates up to a 13× improvement in average accuracy, compared to MSVD without SREA. Figure [3c](https://www.nature.com/articles/s41467-026-76272-2#Fig3) displays RSV numerical error distributions. Vectors solved with SREA have an error standard deviation (σ = 0.192) that is half that of those without SREA (σ = 0.415), suggesting improved precision achieved with SREA. Figure [3d, e](https://www.nature.com/articles/s41467-026-76272-2#Fig3) show the evolutions of the first 3 RSVs and LSVs. These vectors converge accurately in a few iterations, demonstrating our approach’s efficiency.\n\nTo validate the effectiveness of individual SREA components, we conducted an ablation study (Supplementary Fig. [6](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). Dual-precision mapping reduces singular value errors by up to 8.0×, while vector processing refinement achieves up to 3.4× error reduction. To elucidate the principles underlying SREA, we projected the obtained solutions into a two-dimensional parameter space using principal component analysis and derived reconstruction error landscapes at different ranks (Fig. [3f](https://www.nature.com/articles/s41467-026-76272-2#Fig3)). Global landscapes with the trajectories of different methods and individual landscapes at each rank are detailed and analyzed in Supplementary Fig. [7](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) and Note [1](https://www.nature.com/articles/s41467-026-76272-2#MOESM1). The reconstruction error landscapes reveal how SREA and its components influence iterative dynamics. Dual-precision mapping generates steeper landscapes for individual iterations but struggles to establish direct and consistent convergence paths across higher-rank solutions, such as 3<sup>rd</sup>- and 4<sup>th</sup>-rank, due to interference from substantial deflation residuals. Vector processing refinement achieves more thorough deflation, yet systems relying solely on this component experience numerical drift that correlates with flattened landscapes, corresponding to inefficient iterations in higher-rank computations. Through synergistic interaction, SREA creates more effective optimization trajectories than either component alone. These results demonstrate that both SREA components are essential for enhancing MSVD accuracy and enabling effective CIM hardware implementation.\n\n### Low rank approximation\n\nLow-rank approximation is crucial for image and temporal data processing, excelling in compression and feature extraction. We demonstrated the effectiveness of MSVD with SREA (see Supplementary Table [3](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) for detailed configurations) for image enhancement using a 256 × 256 HKU logo (Fig. [4a](https://www.nature.com/articles/s41467-026-76272-2#Fig4)). The image was partitioned into 16×16 blocks and processed via MSVD to retain the top 25% of the ranks (4 ranks for each block). Further enhancement was achieved by scaling the solved top 25% singular values, with varying scaling coefficients producing distinct visual effects. To quantify the reconstruction quality, we employed peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM), as detailed in **Methods**. Compared to software SVD results, MSVD with SREA achieves a maximum PSNR of 31.0 dB and a maximum SSIM of 0.940, showing improvements of up to 4.8 dB in PSNR and 0.114 in SSIM over MSVD without SREA (Fig. [4b, c](https://www.nature.com/articles/s41467-026-76272-2#Fig4)). Compared to neural network-based<sup>[58](https://www.nature.com/articles/s41467-026-76272-2#ref-CR58)</sup> and compressed sensing<sup>[59](https://www.nature.com/articles/s41467-026-76272-2#ref-CR59)</sup> reconstruction methods (Supplementary Fig. [8](https://www.nature.com/articles/s41467-026-76272-2#MOESM1), [9](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)), MSVD-based low-rank reconstruction offers edge-friendly efficiency by avoiding the large-scale parameters and extensive training of neural networks, as well as the complex reconstruction algorithms associated with compressed sensing. For applications demanding higher reconstruction accuracy, system performance can be further enhanced through finer-grained DPM and increased VPR redundancy.\n\nTo validate MSVD’s versatility with temporal data, we applied it to weekly COVID-19 hospital admissions across 51 U.S. states (104 × 51 matrix). The decomposition using the first and second singular vectors reveals varying pandemic trends across states (Fig. [4d, e](https://www.nature.com/articles/s41467-026-76272-2#Fig4)). MSVD with SREA (configurations detailed in Supplementary Table [3](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)) achieves high reconstruction accuracy with mean normalized errors of μ = −4.89 × 10⁻⁵ for the first component and μ = 6.72 × 10⁻³ for the second component. An analysis of correlation coefficients (defined in **Methods**) between reconstructed i-th rank matrices and the software ground truth shows that SREA-enhanced reconstructions achieve coefficients of 0.999 for the first two ranks and 0.995 for the third rank, significantly outperforming MSVD without SREA for higher-rank reconstructions (Fig. [4f](https://www.nature.com/articles/s41467-026-76272-2#Fig4)). This performance arises as SREA mitigates the numerical drifting and component residuals inherent in the power iteration-deflation procedure, thereby improving reconstruction accuracy on each solved rank.\n\nThese results demonstrate that MSVD with SREA achieves performance comparable to software implementations across diverse applications, enabling efficient hardware-based low-rank approximation for real-world image and temporal data processing.\n\n### Incremental learning\n\nSVD is widely used in biomedical signal processing for efficient feature extraction, reducing feature size and computational load. This has led to its integration in wearable medical devices for analyzing physiological signals, such as electromyogram (EMG) and electroencephalogram (EEG). As the user or subject base expands, these systems must classify increasingly diverse signal patterns. However, physiological signals vary significantly between individuals<sup>[60](https://www.nature.com/articles/s41467-026-76272-2#ref-CR60),[61](https://www.nature.com/articles/s41467-026-76272-2#ref-CR61)</sup>, with the same underlying activity producing distinct signal patterns across different users. This variability complicates the application of feature extractors and classifiers trained on existing users to new users.\n\nTo address this challenge, we introduce an incremental MSVD framework for user-scalable recognition (Fig. [5a](https://www.nature.com/articles/s41467-026-76272-2#Fig5)). The approach leverages pre-computed singular components to efficiently accommodate new users. When adding new users, existing RSVs combine with new signals to update components for all users (Fig. [5b](https://www.nature.com/articles/s41467-026-76272-2#Fig5)), allowing the memristor array to compute only with new users’ data and existing RSVs, significantly reducing computational overhead (see **Methods** and Supplementary Fig. [10](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)).\n\nWe first validated this framework on an EMG-based gesture recognition task (Fig. [5c](https://www.nature.com/articles/s41467-026-76272-2#Fig5)). The complete system operates in two phases. During training, MSVD decomposes the EMG training signals to obtain RSVs as a feature extractor, then a linear regression classifier is trained with the extracted features. During inference, memristor-based RSVs process new EMG signals, followed by linear regression for recognition. Since computing singular vectors is the most computationally intensive operation, efficient incremental MSVD substantially improves overall system scalability.\n\nFor this experiment, we used the NinaPro dataset<sup>[62](https://www.nature.com/articles/s41467-026-76272-2#ref-CR62)</sup> with 10-channel EMG signals for 4 gestures, incrementally increasing users from 2 to 8. In each step of adding users, an 864 × 500 EMG signal matrix containing only the new users’ data was incorporated to update the feature extractors (with dimensions of 500 × 6) via incremental MSVD.\n\nMSVD with SREA (configurations detailed in Supplementary Table [3](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)) achieves software-comparable performance. For two users, Fig. [5d](https://www.nature.com/articles/s41467-026-76272-2#Fig5) shows an accuracy of 88.26% averaged over 15 repeats versus 89.58% for software. As users increase (Fig. [5e](https://www.nature.com/articles/s41467-026-76272-2#Fig5)), direct application of 2-user RSVs to 8-users’ signals shows significant accuracy degradation, but incremental MSVD achieves 84.01% average accuracy compared to 64.72% without updates, representing a 19.29% performance recovery. Supplementary Fig. [11](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) presents a comparison between the incremental MSVD-based classification during the user updating and the SVD-based approach on software, where SVD is performed on the cumulative dataset at each corresponding stage. The results demonstrate that incremental MSVD not only restores the accuracy compromised by missing new users’ features but also mitigates the impact of device noise on non-dominant feature components, ultimately achieving software-comparable performance after user updating. The confusion matrix of one typical run on 8-users’ data (Supplementary Fig. [12](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)) confirms robust performance across all gesture classes. RSV analysis (Supplementary Fig. [13](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)) reveals that the first RSV changes minimally as users are added, capturing common signal features, while subsequent vectors adapt to capture individual characteristics.\n\nWe further explored the scalability of incremental MSVD through EEG-based sleep stage detection with a larger cohort of 75 subjects, using a hardware-calibrated simulation framework (Fig. [5g](https://www.nature.com/articles/s41467-026-76272-2#Fig5) and **Methods**). This experiment leveraged the Sleep-EDFx dataset<sup>[63](https://www.nature.com/articles/s41467-026-76272-2#ref-CR63)</sup>, which contains EEG signals recorded from subjects during wakefulness, rapid eye movement (REM) sleep, and deep sleep (non-REM stage 3). In our experiment, EEG signals processed by short-time Fourier transform were fed into the memristor-based system for MSVD/incremental MSVD feature extraction, followed by logistic regression classification. Similar to the EMG-based experiment, at each update, incremental MSVD refined the feature extractor to incorporate all current subjects and updated the classifier accordingly. Both the original data matrix and the incremental updated matrices had dimensions of 900 × 500, each containing information from 15 subjects. MSVD/incremental MSVD yielded RSVs with dimensions of 500 × 5 (solved with 15 iterations per vector) for feature extraction. The SREA configurations for MSVD and incremental MSVD are detailed in Supplementary Table [3](https://www.nature.com/articles/s41467-026-76272-2#MOESM1). After four steps of subject updates, the incremental MSVD-based method achieved a 11.07% performance improvement compared to the non-updated baseline, while the memristor-based system demonstrated performance comparable to software implementation (Fig. [5g](https://www.nature.com/articles/s41467-026-76272-2#Fig5)).\n\nThese results demonstrate that incremental MSVD achieves effective scalable feature extraction without continuously increasing hardware overhead, expanding the practical application scope of MSVD in adaptive computational environments.\n\n### Performance analysis and benchmarking\n\nTo comprehensively evaluate MSVD’s computational advantages beyond the demonstrated accuracy improvements, we conducted systematic performance analysis and benchmarking across multiple datasets. In power iterations, the singular value gap between the target and the subsequent value affects the convergence rate at each rank. Figure [6a](https://www.nature.com/articles/s41467-026-76272-2#Fig6) shows the relationship between convergence iterations and normalized singular value gaps across three datasets (IRIS, COVID-19, and NinaPro). The convergence criterion is set to a relative difference of the temporary squared singular value estimates of less than 2% between consecutive iterations. The results reveal a generally linear trend between the number of convergence iterations and the logarithm of normalized singular value gaps across matrices of varying dimensions and normalized gap ranges from 10<sup>0</sup> to 10<sup>−3</sup> (Supplementary Table [4](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)), demonstrating the scalability of MSVD with SREA. The results also confirm that MSVD with SREA consistently requires fewer iterations to achieve convergence compared to MSVD without SREA across all problem scales, further demonstrating SREA’s superiority in accelerating convergence. Detailed convergence analysis on individual datasets is presented in Supplementary Fig. [14](https://www.nature.com/articles/s41467-026-76272-2#MOESM1). Additionally, Supplementary Note [2](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) provides a theoretical analysis of the resolution limits of MSVD based on Wedin’s law<sup>[64](https://www.nature.com/articles/s41467-026-76272-2#ref-CR64)</sup>. This discussion suggests that the normalized spectral gap of a specific problem, formulated as $({s}_{i}-{s}_{i+1})/{s}_{1}$, along with inherent system errors, jointly influences the minimum resolvable singular value in MSVD.\n\nFor single SVD computation efficiency, MSVD with SREA demonstrates substantial computational advantages. Compared to MSVD without SREA, SREA provides 48.5% energy savings and 48.1% speed improvements through convergence acceleration (**Methods**). Against conventional graphics processing unit (GPU) implementations, the advantages are even more pronounced, achieving 29.9× energy efficiency improvement and 19.0× speed enhancement in EMG signal recognition tasks (Fig. [6b, c](https://www.nature.com/articles/s41467-026-76272-2#Fig6)). Computation energy and area breakdowns for MSVD implementation are shown in Fig. [6d, e](https://www.nature.com/articles/s41467-026-76272-2#Fig6), revealing the contributions of analog-digital converters, memristor arrays, drivers and other circuits.\n\nIn incremental learning scenarios, the computational advantages become even more significant. For user-scalable EMG recognition involving progressive data updates from 2 to 8 users, incremental MSVD exhibits 67.1× energy reduction and 39.7× speed improvement on average compared to conventional GPU approaches (Fig. [6f, g](https://www.nature.com/articles/s41467-026-76272-2#Fig6)). As the number of updates increases, these advantages grow substantially, achieving up to 89.6× energy savings and 57.3× speedup in the third update cycle. Even within incremental scenarios, MSVD with SREA maintains 42.4% energy savings and 45.3% speedup advantages over MSVD without SREA (**Methods**, Supplementary Fig. [15](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). These results demonstrate the efficiency of our approach for both low-rank information processing and incremental data handling in wearable medical applications.\n\n### Initialization in large language model fine-tuning\n\nTo further investigate the scalability of MSVD and SREA in large-scale applications, we evaluated their performance on the parameter-efficient fine-tuning of LLMs through simulation. As the scale of language models continues to grow, low-rank adaptation<sup>[13](https://www.nature.com/articles/s41467-026-76272-2#ref-CR13)</sup> has emerged as a crucial technique, which mitigates prohibitive training costs by freezing the dense weights and introducing small, trainable low-rank matrices to capture task-specific updates. Crucially, initializing these matrices via SVD<sup>[15](https://www.nature.com/articles/s41467-026-76272-2#ref-CR15),[16](https://www.nature.com/articles/s41467-026-76272-2#ref-CR16)</sup> explicitly extracts the principal components of the pre-trained weights, effectively accelerating convergence and enhancing final performance. Along with the rapid development of memristor-based language model fine-tuning accelerators<sup>[65](https://www.nature.com/articles/s41467-026-76272-2#ref-CR65)</sup>, executing efficient SVD directly on memristors has become highly critical to further optimize the initialization overhead and streamline the entire fine-tuning pipeline.\n\nHere, we employed the hardware-calibrated simulation framework to demonstrate principal singular values and singular vectors adaptation<sup>[15](https://www.nature.com/articles/s41467-026-76272-2#ref-CR15)</sup> (PiSSA), a representative low-rank adaptation method that we specifically initialize with MSVD (Fig. [7a, b](https://www.nature.com/articles/s41467-026-76272-2#Fig7)). In this approach, all static weights within the model (with dimensions such as 2048 × 2048 and 2048 × 512, detailed in Supplementary Table [5](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)) underwent rank-4 decomposition. The resulting matrices ${{{\\boldsymbol{U}}}}$, ${{{\\boldsymbol{S}}}}$, and ${{{\\boldsymbol{V}}}}$ were then utilized to construct the branches for subsequent fine-tuning (see **Methods** for details).\n\nWe applied MSVD-based PiSSA, with SREA (configurations detailed in Supplementary Table [3](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)), to fine-tune LLaMA 3.2 models<sup>[66](https://www.nature.com/articles/s41467-026-76272-2#ref-CR66)</sup> (1B and 3B) on the MetaMathQA<sup>[67](https://www.nature.com/articles/s41467-026-76272-2#ref-CR67)</sup> dataset for two and one epoch, respectively, and then evaluated them on the GSM8K<sup>[53](https://www.nature.com/articles/s41467-026-76272-2#ref-CR53)</sup> and MATH<sup>[54](https://www.nature.com/articles/s41467-026-76272-2#ref-CR54)</sup> datasets. The loss curves and gradient norms (Supplementary Fig. [16](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)) during fine-tuning indicate that MSVD-based PiSSA effectively accelerates fine-tuning progress compared to the vanilla adaptation method, while maintaining optimization dynamics that closely align with the software-based PiSSA baseline. Regarding mathematical problem-solving capabilities, on the GSM8K (Fig. [7c](https://www.nature.com/articles/s41467-026-76272-2#Fig7)) and MATH (Fig. [7d](https://www.nature.com/articles/s41467-026-76272-2#Fig7)) benchmarks, MSVD-based PiSSA achieves results comparable to its software counterpart (e.g., 26.41 vs. 26.61 and 51.25 vs. 51.40 on GSM8K for 1B and 3B, respectively). Moreover, it consistently outperforms the vanilla method, improving the GSM8K score from 24.11 to 26.41 (a 9.5% relative gain) for the 1B model and from 46.40 to 51.25 (a 10.5% relative gain) for the 3B model. Supplementary Fig. [17](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) presents an ablation study of SREA on LLaMA 3.2-1B. The introduction of SREA yields a performance improvement of 1.09 points (a 4.3% relative gain) on the GSM8K dataset and 0.42 points (an 8.3% relative gain) on the MATH dataset, further confirming the efficacy of SREA in large-scale tasks. Figure [7e, f](https://www.nature.com/articles/s41467-026-76272-2#Fig7) illustrate the energy efficiency and normalized speed of MSVD-based initialization compared to GPUs. At the 32 nm technology node, the memristor-based system achieves a 41.6× advantage in energy efficiency and a 23.1× speedup relative to GPUs (see Supplementary Fig. [18](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) for the system-level energy and area breakdown of MSVD-based initialization on the LLaMA 3.2 1B and 3B models). These results collectively demonstrate the scalability of MSVD to larger workloads and its feasibility for practical LLM applications.\n\n## Discussion\n\nIn summary, we present an energy-efficient and high-fidelity MSVD for low-rank representation. Through carefully designed SREA incorporating dual-precision mapping and vector processing refinement, we have effectively optimized the multi-scale iterative computation process on memristors. Experimental demonstrations across image reconstruction, temporal data analysis, biomedical signal processing and efficient LLM fine-tuning show that our approach achieves software-comparable accuracy. The incremental MSVD framework further highlights the data processing capabilities of this method in adaptive computing scenarios. Moreover, compared with conventional CMOS implementations, the proposed system exhibits substantial advantages in both energy efficiency and computational speed.\n\nThese results establish the potential of MSVD as a general decomposition tool, especially for resource-constrained applications including wearable medical devices and edge artificial intelligence systems. Our work demonstrates a viable approach for memristor-based CIM to handle multi-scale iterative algorithms, thus extending memristor-based computing capabilities towards broader scientific computing and machine learning applications.\n\n## Methods\n\n### Implementation of memristive singular value decomposition\n\nThe SVD of a data matrix ${{{\\boldsymbol{X}}}}\\in {{\\mathbb{R}}}^{M\\times N}$ can be mathematically defined as ${{{\\boldsymbol{X}}}}={{{\\boldsymbol{US}}}}{{{{\\boldsymbol{V}}}}}^{T}$, where ${{{\\boldsymbol{U}}}}\\in {{\\mathbb{R}}}^{M\\times M}$, ${{{\\boldsymbol{V}}}}\\in {{\\mathbb{R}}}^{N\\times N}$ and ${{{\\boldsymbol{S}}}}\\in {{\\mathbb{R}}}^{M\\times N}$ are the matrices of LSVs, RSVs and singular values, respectively. Consequently, the data covariance matrix ${{{{\\boldsymbol{X}}}}}^{T}{{{\\boldsymbol{X}}}}\\in {{\\mathbb{R}}}^{N\\times N}$ can be expressed as ${{{{\\boldsymbol{X}}}}}^{T}{{{\\boldsymbol{X}}}}={{{\\boldsymbol{V}}}}{{{{\\boldsymbol{S}}}}}^{2}{{{{\\boldsymbol{V}}}}}^{T}{{{\\boldsymbol{.}}}}$\n\nSince the columns of ${{{\\boldsymbol{V}}}}$ (denoted as ${{{{\\boldsymbol{v}}}}}_{i}$) form an orthonormal basis for ${{\\mathbb{R}}}^{N}$, any randomly initialized input vector ${v}_{{in}}$ can be represented as a linear combination of these basis vectors:\n\nwhere ${c}_{i}$ are scalar coefficients. Thus, the iteratively multiplying ${{{{\\boldsymbol{X}}}}}^{T}{{{\\boldsymbol{X}}}}$ by ${{{{\\boldsymbol{v}}}}}_{{{{\\rm{in}}}}}$ for $k$ times yields:\n\nwhere ${s}_{i}$ is the $i$-th diagonal value in matrix ${{{\\boldsymbol{S}}}}$, and ${s}_{1} > {s}_{2} > \\ldots > {s}_{N} > 0$. As $k\\to \\infty$, the terms ${\\left(\\frac{{s}_{i}}{{s}_{1}}\\right)}^{2k}$ for $i\\ge 2$ approach 0. Therefore, the first RSV can be extracted from ${{{{\\boldsymbol{v}}}}}_{1}={{{\\rm{norm}}}}\\left({\\left({{{{\\boldsymbol{X}}}}}^{T}{{{\\boldsymbol{X}}}}\\right)}^{k}{{{{\\boldsymbol{v}}}}}_{{{{\\rm{in}}}}}^{\\left(1\\right)}\\right)$.\n\nIn the practical implementation, the$\\,{{{{\\boldsymbol{v}}}}}_{1}$ is obtained through iteration loop. Starting with the randomly initialized intermediate vector ${\\widetilde{{{{\\boldsymbol{v}}}}}}_{1}$, the update rule is executed as follows:\n\nwhere ${{{\\rm{norm}}}}()$ denotes the normalization operation executed on CPU. The process continues until convergence or the maximum iteration limit is reached. The solved ${{{{\\boldsymbol{v}}}}}_{1}$ is then stored in an additional array to construct the matrix ${{{\\boldsymbol{V}}}}$ and the first singular value can be computed as ${{s}_{1}^{2}={{{\\boldsymbol{v}}}}}_{1}^{T}{{{{\\boldsymbol{X}}}}}^{T}{{{\\boldsymbol{X}}}}{{{{\\boldsymbol{v}}}}}_{1}$.\n\nTo extract subsequent singular vectors and singular values, components related to previously computed singular vectors must be deflated. The power iteration-deflation approach for $i$-th singular vector ${{{{\\boldsymbol{v}}}}}_{i}$ is executed in each loop as:\n\nwhere ${\\widetilde{{{{\\boldsymbol{v}}}}}}_{i}$ is the randomly initialized intermediate vector, ${{{{\\boldsymbol{S}}}}}_{i-1}$ is the diagonal matrix containing the first $i-1$ singular values which scales the output of multiplication ${{{{\\boldsymbol{V}}}}}_{i-1}^{T}{\\widetilde{{{{\\boldsymbol{v}}}}}}_{i}$. Additionally, ${{{{\\boldsymbol{S}}}}}_{0}$ and ${{{{\\boldsymbol{V}}}}}_{0}$ are defined as zero matrices. The solved ${{{{\\boldsymbol{v}}}}}_{i}$ is subsequently updated to ${{{\\boldsymbol{V}}}}$, and the $i$-th singular value is obtained from:\n\nBased on the properties of SVD, since the ${{{{\\boldsymbol{v}}}}}_{i}$ are mutually orthogonal (i.e., ${{{{\\boldsymbol{V}}}}}^{-1}={{{{\\boldsymbol{V}}}}}^{{{{\\boldsymbol{T}}}}}$), the corresponding LSVs can be directly derived as:\n\nThrough these iterative processes, the power-iteration deflation for MSVD is completed. The flowchart of the MSVD process is illustrated in Supplementary Fig. [19](https://www.nature.com/articles/s41467-026-76272-2#MOESM1). During computation, the data matrix ${{{\\boldsymbol{X}}}}$ and the computed RSVs (${{{\\boldsymbol{V}}}}$) are stored on the memristor crossbar arrays to perform the multiplications. The auxiliary operations, including element-wise vector multiplication (for ${{{{\\boldsymbol{S}}}}}^{2}$ scaling of RSV inputs), subtraction, normalization (for deflation), and convergence detection, are implemented on the FPGA and CPU. At the beginning of each power iteration-deflation stage, the iterative processes on both matrices (${{{\\boldsymbol{X}}}}$ and ${{{\\boldsymbol{V}}}}$) start with the same randomly initialized input vector ${{\\widetilde{{{{\\boldsymbol{v}}}}}}_{i}={{{\\boldsymbol{v}}}}}_{{{{\\rm{in}}}}}$, and the iterative vector-matrix multiplications described in Eq. ([4](https://www.nature.com/articles/s41467-026-76272-2#Equ4)) are then performed in situ on the arrays. To prevent excessive iterations, the maximum iteration count is restricted to fewer than 30. The LSVs (${{{\\boldsymbol{U}}}}$) are obtained via matrix–vector multiplication with the data matrix as expressed in Eq. ([6](https://www.nature.com/articles/s41467-026-76272-2#Equ6)) and therefore do not require additional on-array storage.\n\n### Dual precision mapping\n\nIn the dual-precision mapping strategy, each number to be mapped to memristors is divided into a high-order part with low resolution and a low-order part with high resolution. For example, 8-bit vectors ${{{\\boldsymbol{X}}}}$ and ${{{\\boldsymbol{Y}}}}$ can be divided into high-order 2 bits and low-order 6 bits as follows:\n\nwhere $h$ and $l$ represent the bit numbers of high-order and low-order parts, respectively. The multiplication of ${{{\\boldsymbol{X}}}}$ and ${{{\\boldsymbol{Y}}}}$ can be expressed as:\n\nwhere $\\ll l$ denotes left bit shift by $l$ positions to restore the proper magnitude of the high-order contribution.\n\nThis approach ensures that the output of high-order part remains accurate after quantization, which minimizes the amplification of high-order errors by significance weight and thereby increases the stability of convergence in MSVD. Meanwhile, the higher-resolution low-order part retains the capability to express fine numerical details during computation, making the convergence results closer to actual values. The detailed DPM setting in different experiments is shown in Supplementary Table [3](https://www.nature.com/articles/s41467-026-76272-2#MOESM1). Simulation-based studies and analysis, detailed in Supplementary Fig. [20](https://www.nature.com/articles/s41467-026-76272-2#MOESM1), [21](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) and Note [3](https://www.nature.com/articles/s41467-026-76272-2#MOESM1), further demonstrate the validity and effectiveness of the DPM.\n\n### Vector processing refinement\n\nTo implement the VPR strategy, we adjust the input precision and employ spatial replication specifically for the RSVs. First, during the second vector-matrix multiplication of each power iteration loop (Eq. [4](https://www.nature.com/articles/s41467-026-76272-2#Equ4)), the input vectors to the RSV matrix are encoded with a higher bit-width than the standard system precision (see Supplementary Table [3](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) for detailed configurations). As these inputs, scaled by ${s}_{i}^{2}$, possess a significantly larger dynamic range, standard quantization errors would otherwise be amplified in subsequent multiplications and degrade the final accuracy. This elevated precision thus preserves representational expressiveness and mitigates cumulative quantization errors (see Supplementary Note [4](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) and Supplementary Fig. [22](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) for analysis). Second, to physically suppress memristor mapping deviations and reading fluctuations (whose effects on the deflation output would also be amplified by the scaled inputs), the RSVs are spatially replicated across the memristor array, and their outputs are averaged to yield noise-reduced results.\n\nThis method maintains elevated bit precision only for essential inputs and replicates only the small-sized singular vectors during mapping. Consequently, it ensures deflation process fidelity while incurring significantly lower energy and area overheads compared to a globally high-precision and replicated mapping of all matrices.\n\n### Customized memristor hardware platform and architecture\n\nWe fabricated the memristor chip using a 130 nm technology node. The chip features a 1024 × 128 one-transistor-one-resistor (1T1R) memristor array, and Si CMOS peripheral circuits. Each 1T1R cell comprises a memristor (0.5 µm × 0.5 µm) with a TiN/TaO<sub>x</sub>/HfO<sub>2</sub>/TiN material stack and an access transistor. The layer composition includes an 8 nm HfO<sub>2</sub> resistive switching layer deposited by atomic layer deposition, a 45 nm sputtered TaO<sub>x</sub> thermal enhancement layer, and 30 nm sputtered TiN top/bottom electrodes (shown in transmission electron microscope image in Supplementary Fig. [4a](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). Peripheral circuits, including input buffers, drivers, shift registers, and decoders, support read/write operations and enable fully parallel computation (detailed in Supplementary Fig. [3](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). To ensure precise conductance mapping, multiple voltage pulses are applied to each 1T1R memristor cell using a standard write-verify scheme, incrementally adjusting conductance until target values are reached within the error margin. The demonstration employs a customized system featuring a three-layer printed-circuit-board stack configuration, comprising a memristor board, a power board, and a field-programmable gate array (FPGA, Xilinx, ZCU102) board (Supplementary Fig. [2a](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). The system digitally encodes input data into a temporal sequence of 50 ns 1-bit voltage pulses (0.2 V representing ‘1’ and 0 V representing ‘0’), which are applied to the array to perform vector-matrix multiplication. We designed a dedicated architecture that enables complete MSVD processing through coordinated operations between the memristor CIM macro for matrix multiplications and the FPGA controller for iteration management (detailed architecture design and dataflow in Supplementary Fig. [2b](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)).\n\n### Data mapping and experiment configuration\n\nA write–verify scheme is employed to program the conductance of the memristor devices, as illustrated in Supplementary Fig. [23](https://www.nature.com/articles/s41467-026-76272-2#MOESM1). The linearly quantized data (Supplementary Note [5](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)) are programmed by applying SET/RESET voltage pulses ranging from 0.5 V to 2 V, followed by a read verification step at 0.2 V. This write–verify cycle is repeated until the read current falls within the target threshold range. Supplementary Fig. [24](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) details the relative voltage configurations applied to the WL, SL, and BL of the selected cell during the SET, RESET, and read operations, respectively. To accommodate both positive and negative matrix elements, a differential mapping scheme is adopted. Benefiting from the high yield of our devices ( ~ 99.99%), the impact of stuck-at faults on MSVD is minimal (as analyzed in Supplementary Fig. [25](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)), eliminating the need for complex fault-tolerant mapping strategies.\n\nSupplementary Fig. [26](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) illustrates how the data matrix and the computed RSVs are mapped onto a single macro for implementing MSVD with SREA. The input data matrix is programmed onto the array at the start of computation, and the solved RSVs are subsequently written onto the array as the decomposition proceeds. The DPM scheme partitions the data matrix and RSVs into two segments, whereas VPR replicates the RSVs several times on the array. Detailed SREA configurations for each experiment are provided in Supplementary Table [3](https://www.nature.com/articles/s41467-026-76272-2#MOESM1).\n\nConstrained by the scale of our testing platform, for the image low-rank reconstruction and EMG-based gesture recognition tasks, we employed a reprogramming strategy to acquire the device conductances of the full matrix. We then conducted experiments by simulating the larger-scale peripheral circuits based on these measurements. Furthermore, we propose a multi-macro architecture (shown in Supplementary Fig. [27](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)), which serves as a reference for larger-scale deployments utilizing multiple macros. For EEG-based sleep stage detection task and low-rank adaptation with MSVD initialization, we utilize a hardware-calibrated simulation framework that incorporates a noise-aware memristor model and peripheral circuit models (including quantization and shift-and-add operations) to emulate a larger memristor-based computing system. During these experiments, the device conductance mapping range is set from 0 to 30 μS. The device read and write variations are modeled as Gaussian-distributed noise based on our actual device measurements (Fig. [2g](https://www.nature.com/articles/s41467-026-76272-2#Fig2)) to ensure fidelity.\n\n### Low rank approximation metrics for image and temporal data\n\nTo evaluate the quality of reconstructed images and data with principal components, we use widely accepted metrics: PSNR, SSIM, and correlation coefficient.\n\nFor an RGB image ${{{\\boldsymbol{I}}}}$ with dimensions $m\\times n\\times 3$, where ${{{\\boldsymbol{K}}}}$ is the low-rank approximation of ${{{\\boldsymbol{I}}}}$, PSNR is defined as:\n\nwhere ${{{{\\rm{MAX}}}}}_{{{{\\boldsymbol{I}}}}}$ is the maximum pixel value of image ${{{\\boldsymbol{I}}}}$, and ${{{\\rm{MSE}}}}$ is the mean squared error averaged across all RGB channels\n\nwhere ${{{{\\boldsymbol{I}}}}}_{{{{\\rm{ch}}}}}$ and ${{{{\\boldsymbol{K}}}}}_{{{{\\rm{ch}}}}}$ represent specific channels of image ${{{\\boldsymbol{I}}}}$ and ${{{\\boldsymbol{K}}}}$, respectively.\n\nSSIM is computed as:\n\nwhere ${C}_{1}=6.5025$, ${C}_{2}=58.5225$; ${\\mu }_{{{{\\boldsymbol{K}}}},{{{\\rm{ch}}}}}$, ${\\mu }_{{{{\\boldsymbol{I}}}},{{{\\rm{ch}}}}}$,${\\sigma }_{{{{\\boldsymbol{K}}}},{{{\\rm{ch}}}}}$, ${\\sigma }_{{{{\\boldsymbol{I}}}},{{{\\rm{ch}}}}}$, ${\\sigma }_{{{{\\boldsymbol{KI}}}},{{{\\rm{ch}}}}}$ are local means, standard deviations and cross-covariance of the corresponding channels in images ${{{\\boldsymbol{K}}}}$ and ${{{\\boldsymbol{I}}}}$.\n\nFor the temporal data matrices ${{{\\boldsymbol{X}}}}$ and ${{{\\boldsymbol{Y}}}}$ with dimensions $m\\times n$, the correlation coefficient is calculated as:\n\nwhere ${\\mbox{mean}}(\\cdot )$ denotes the average value of all elements in the given matrix.\n\n### Incremental decomposition for gesture recognition\n\nIncremental MSVD is designed to obtain the updated RSVs for the tasks with incremental added data matrices. Building upon the implemented MSVD, when the input data expands from existing data ${{{{\\boldsymbol{X}}}}}_{{{{\\rm{exist}}}}}$ to ${{{\\boldsymbol{X}}}}^{{{\\prime} }}=\\left[\\begin{array}{c}{{{{\\boldsymbol{X}}}}}_{{{{\\rm{new}}}}}\\\\ {{{{\\boldsymbol{X}}}}}_{{{{\\rm{exist}}}}}\\end{array}\\right]$, the updated data covariance matrix ${{{{\\boldsymbol{X}}}}^{{{\\prime} }}}^{T}{{{\\boldsymbol{X}}}}^{{{\\prime} }}$ can be approximated by combining the newly added component with the low-rank approximation of the existing component:\n\nwhere ${{{{\\boldsymbol{V}}}}}_{{{{\\rm{exist}}}}}$ represents previously solved RSVs.\n\nIn practical implementations, each updated RSV ${{{{\\boldsymbol{v}}}}}_{i}^{{\\prime} }$ can be obtained through an iteration loop. Starting with a randomly initialized intermediate vector ${\\widetilde{{{{\\boldsymbol{v}}}}}}_{i}^{{\\prime} }$, the power iteration-deflation approach is executed in each loop as:\n\nwhere ${{{\\boldsymbol{V}}}}^{{{\\prime} }}$ and ${{{\\boldsymbol{S}}}}^{{{\\prime} }}$ are the updated matrices of RSVs and singular values, respectively. And $i$-th singular value in current stage is obtained with:\n\nOn the hardware platform, we maintain an additional memristor array to store the previously solved RSVs. When new data arrives, it is mapped to the data array, and the previously solved in-memory RSVs (${{{{\\boldsymbol{V}}}}}_{{{{\\rm{exist}}}}}$) are used to represent existing data and calculate updated RSVs. During the continuous solving process, both ${{{{\\boldsymbol{V}}}}}_{{{{\\rm{exist}}}}}$ and ${{{\\boldsymbol{V}}}}^{{{\\prime} }}$ are stored on the array. In each new round of incremental MSVD (e.g., when updating user data matrix), the previously computed ${{{\\boldsymbol{V}}}}^{{{\\prime} }}$ serves as the new ${{{{\\boldsymbol{V}}}}}_{{{{\\rm{exist}}}}}$, while the newly solved RSVs are overwritten onto the region that originally stored the previous ${{{{\\boldsymbol{V}}}}}_{{{{\\rm{exist}}}}}$.\n\n### Benchmarks of energy efficiency\n\nEnergy consumption is evaluated with the architecture detailed in Supplementary Fig. [2](https://www.nature.com/articles/s41467-026-76272-2#MOESM1), which contains memristor array and peripheral circuits. We evaluated energy consumptions using verified designs and XPESim<sup>[68](https://www.nature.com/articles/s41467-026-76272-2#ref-CR68)</sup> based on a mature memristor-embedded 32 nm technology. For the EMG-based gesture recognition task, the system was configured with a [3,5] DPM division, 4-times vector repetition and 10 additional input bits for VPR alongside basic 8-bit input. Furthermore, 15 iterations are considered for each rank decomposition. Under these settings, a single MSVD computation consumes 13.40 μJ, while one incremental MSVD update consumes 17.83 μJ (detailed in Supplementary Note [6](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) and Supplementary Table [6](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). For comparison, the energy efficiency of a representative Nvidia A100 GPU is 390 GOPS⋅W<sup>-1</sup>. With 156 M operations required, the energy consumption for singular vector solving on GPU is 400 μJ. Consequently, MSVD demonstrates a 29.9× energy efficiency advantage over the GPU (13.40 μJ vs. 400 μJ). Even at the 130 nm technology node, MSVD maintains a 10× advantage in energy efficiency (Supplementary Fig. [28](https://www.nature.com/articles/s41467-026-76272-2#MOESM1), Note [7](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). For the incremental learning with singular vector updating processes, GPU energy consumption using conventional approaches is 799 μJ, 1197 μJ, and 1597 μJ for the first, second, and third updates, respectively (detailed in Supplementary Note [6](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). Incremental MSVD achieves up to 89.6× advantage (17.83 μJ vs 1597μJ, during the third update process), and overall 67.1× energy consumption reduction ((799 + 1197 + 1597) / (17.83 × 3) = 67.1).\n\nCompared to an application-specific integrated circuit (ASIC) designed for high performance computing (Google TPUv3), incremental MSVD achieves a 55.9× overall energy efficiency advantage (Supplementary Fig. [29](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). Supplementary Table [7](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) further presents an energy efficiency comparison against other CMOS-based decomposition ASICs; despite variations in task scale, the advantage of MSVD remains evident. Additionally, energy benchmarking performed on incremental MSVD for EEG-based sleep stage detection demonstrates a 57.3× advantage (84.6 μJ vs. 4852 μJ) over the A100 GPU and a 47.7× advantage (84.6 μJ vs. 4035 μJ) over the Google TPUv3 (Supplementary Fig. [30](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)).\n\nComparisons of energy consumption between implementations with SREA and without SREA are provided in Supplementary Note [6](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) and Supplementary Table [6](https://www.nature.com/articles/s41467-026-76272-2#MOESM1). By reducing the number of iterations required for convergence, SREA yields a 48.5% energy saving (13.40 μJ versus 26.04 μJ) for MSVD and 42.4% for incremental MSVD (17.83 μJ versus 30.97 μJ), demonstrating that SREA’s optimization of the solving process effectively enhances energy efficiency of decomposition. The energy breakdown of each system module across tasks of different scales is further shown in Supplementary Fig. [31](https://www.nature.com/articles/s41467-026-76272-2#MOESM1).\n\n### Benchmark of normalized speed\n\nNormalized speed is evaluated by the speed of operations divided by the chip area required. With a parallel operating paradigm, delays of MSVD with and without SREA are 183.8 μs and 280.5 μs in EMG-based gesture recognition task, respectively. (See Supplementary Note [8](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) and Supplementary Tables [8](https://www.nature.com/articles/s41467-026-76272-2#MOESM1), [9](https://www.nature.com/articles/s41467-026-76272-2#MOESM1) for details.) The total areas required for MSVD with and without SREA are 0.236 mm<sup>2</sup> and 0.229 mm<sup>2</sup> respectively (the area breakdown of each system module across tasks of different scales is shown in Supplementary Fig. [31](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). Based on these metrics, the normalized solving speed of MSVD with SREA is 23054 computations·s⁻¹·mm⁻², while MSVD without SREA achieves 15568 computations·s<sup>-1</sup>·mm<sup>-2</sup>. Consequently, SREA accelerates MSVD by 48.1%. For A100 GPU with 156 TOPS computing power and 826 mm<sup>2</sup> die size, the normalized solving speed is 1211 computations·s<sup>-1</sup>·mm<sup>-2</sup>. Thus, our MSVD demonstrates a 19.0× advantage in normalized computing speed. Additionally, regarding the speed comparison against CMOS-based ASICs, as shown in Supplementary Table [7](https://www.nature.com/articles/s41467-026-76272-2#MOESM1), MSVD exhibits a notable lead, despite the difference in problem size.\n\nWith memristor arrays of data matrix, pre-computed vectors, vectors to be computed operating in parallel, the delay of operations on pre-computed vectors can be hidden within the concurrent operations on the other two matrices, introducing no additional overhead. The areas of incremental MSVD with and without SREA are 0.313 mm<sup>2</sup> and 0.298 mm<sup>2</sup> respectively (Supplementary Table [8](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). For each update, incremental MSVD with and without SREA achieves normalized speeds of 17382 updates·s<sup>-1</sup>·mm<sup>-2</sup> and 11963 updates·s<sup>-1</sup>·mm<sup>-2</sup> while the GPU’s speeds are 607, 404, and 303 updates·s<sup>-1</sup>·mm<sup>-2</sup> for the three updates, respectively (detailed in Supplementary Note [8](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). Consequently, incremental MSVD achieves an average 39.7× speedup advantage, with up to 57.3× advantage across three updates. Meanwhile, SREA accelerates incremental MSVD by 45.3%.\n\nCompared to Google TPUv3 (~700 mm<sup>2</sup> estimated die size<sup>[69](https://www.nature.com/articles/s41467-026-76272-2#ref-CR69)</sup>), incremental MSVD exhibits a 42.6× average speed improvement (17382 updates·s<sup>−1</sup>·mm<sup>-2</sup> vs. 408 updates·s<sup>-1</sup>·mm<sup>-2</sup>, Supplementary Fig. [29](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)). Additionally, in the context of EEG-based sleep stage detection, incremental MSVD demonstrates a 21.0× average speedup (8744 updates·s<sup>-1</sup>·mm<sup>-2</sup> vs. 416 updates·s<sup>-1</sup>·mm<sup>-2</sup>) relative to the TPUv3 (Supplementary Fig. [30](https://www.nature.com/articles/s41467-026-76272-2#MOESM1)).\n\n### Initialization for low rank adaptation\n\nLow-rank adaptation techniques typically partition the pre-trained model weights into two distinct components: a frozen (untrainable) residual matrix $\\in {{\\mathbb{R}}}^{M\\times N}$, and two trainable low-rank branches, denoted as ${{{\\rm{Branc}}}}{{{{\\rm{h}}}}}_{{{{\\rm{A}}}}}\\in {{\\mathbb{R}}}^{r\\times N}$ and ${{{\\rm{Branc}}}}{{{{\\rm{h}}}}}_{{{{\\rm{B}}}}}\\in {{\\mathbb{R}}}^{M\\times r}$, where $r$ represents the target low rank.\n\nIn our approach, we utilize MSVD to initialize these components. Specifically, we apply MSVD to the static weights in each transformer layer of LLMs, including the query, key, and value layers, the output-projection, up-projection, down-projection, and the gate layers, as illustrated in Fig. [7a](https://www.nature.com/articles/s41467-026-76272-2#Fig7). For each weight matrix, we perform a rank-4 MSVD, executing 15 iterations per rank. The resulting decomposition factors are then used to construct the PiSSA weight initialization. The trainable low-rank branches are formed as:\n\nwhere ${{{\\boldsymbol{S}}}}$, ${{{\\boldsymbol{V}}}}$, ${{{\\boldsymbol{U}}}}$ represent solved singular values, right singular vectors and left singular vectors, respectively. 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The design process for Google’s training chips: TPUv2 and TPUv3. *IEEE Micro***41** , 56–63 (2021).\n\n## Funding\n\nThis research was supported in part by the Theme-based Research Scheme (TRS) project T45-701/22-R and the General Research Fund (GRF) 17200925 of the Research Grants Council (RGC), Hong Kong SAR, in part by the National Natural Science Foundation of China Project 62404187, and in part by the Shenzhen Science and Technology Program (Grant No. JCYJ20220818100217038).\n\n## Ethics declarations\n\n### Competing interests\n\nThe authors declare no competing interests.\n\n## Peer review\n\n### Peer review information\n\n*Nature Communications* thanks Martin Lueker-Boden who co-reviewed with Osama Yousuf, Amirali Amirsoleimani and the other anonymous reviewer(s) for their contribution to the peer review of this work. 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To view a copy of this licence, visit [http://creativecommons.org/licenses/by-nc-nd/4.0/](http://creativecommons.org/licenses/by-nc-nd/4.0/).\n\n## About this article\n\n### Cite this article\n\nDing, C., Liu, Z., Zhang, Y. *et al.* Memristive singular value decomposition.\n                    *Nat Commun* **17**, 8006 (2026). https://doi.org/10.1038/s41467-026-76272-2\n\n- Received:\n- Accepted:\n- Published:\n- Version of record:\n- DOI: https://doi.org/10.1038/s41467-026-76272-2", "url": "https://wpnews.pro/news/memristive-singular-value-decomposition", "canonical_source": "https://www.nature.com/articles/s41467-026-76272-2", "published_at": "2026-09-23 11:00:55+00:00", "updated_at": "2026-09-23 11:31:19.917511+00:00", "lang": "en", "topics": ["machine-learning", "ai-infrastructure", "large-language-models", "ai-research"], "entities": ["MSVD", "SREA", "compute-in-memory", "memristor", "Singular value decomposition", "large language model"], "alternates": {"html": "https://wpnews.pro/news/memristive-singular-value-decomposition", "markdown": "https://wpnews.pro/news/memristive-singular-value-decomposition.md", "text": "https://wpnews.pro/news/memristive-singular-value-decomposition.txt", "jsonld": "https://wpnews.pro/news/memristive-singular-value-decomposition.jsonld"}}