LightSwitch – In-Network and Photonic LLM Inference in Transit

Project LightSwitch, an experimental software prototype and hardware architecture, claims to enable in-network and photonic LLM inference by embedding intelligence directly into light traveling through global networks, reducing compute energy by 95%-98% and eliminating GPU memory bottlenecks. The project, which uses 1.58-bit ternary additive transforms and commercial off-the-shelf hardware like AMD Xilinx UltraScale+ FPGA SmartNICs and Intel Tofino 2 P4 switches, simulates executing inference inside optical fibers and satellite laser links while packets are in transit.

"Do not send data to centralized AI data centers: embed intelligence directly into the light traveling through global networks." 📖 Languages : English | 🇮🇹 Leggi in Italiano Italian Version /pisantifrancesco89/Project-LightSwitch/blob/main/README IT.md Project LightSwitch is an experimental software prototype and hardware architecture for In-Network & Photonic Artificial Intelligence Compute . It simulates executing Large Language Model LLM inference and matrix transformations directly inside optical fibers, switching cabins, and satellite laser links while packets are in transit, eliminating the GPU Von Neumann memory bottleneck and reducing compute energy by $95% - 98%$ . CLIENT Copper / Wi-Fi ↓ Tokenized prompt SWITCHING CABIN / EDGE PoP P4 Switch / FPGA ➔ Computes Initial Model Layers 15 ns ↓ WDM Optical Carrier Modulation @ 1550nm C-Band TERRESTRIAL & SUBMARINE OPTICAL FIBER ➔ Photons travel at 200,000 km/s in silica ↓ Ternary Optical Phase Interference {-1, 0, 1} LEO SATELLITE CONSTELLATION ➔ Inter-satellite laser links at 300,000 km/s Speed of light in vacuum ↓ Downlink & Token Decapsulation DESTINATION GATEWAY ➔ Final output token already computed upon arrival Zero GPU queue latency - Zero Multiplications : Model weights are quantized to 1.58-bit $100%$ Additive Transforms ${-1, 0, 1}$ . Floating-point multiplications are replaced by optical constructive/destructive phase interference and integer add/subtract operations $0\text{ FP Multiplications}$ . - Zero VRAM Bottleneck : Static weight matrices reside in on-chip routing tables TCAM / UltraRAM / Micro-Ring Resonators , eliminating power-hungry HBM memory transfers. - Sub-2 Nanosecond Hardware Packet Filter : Switches inspect incoming headers in, instantly distinguishing AI prompt packets from everyday Internet traffic Netflix, Zoom, HTTPS without CPU intervention.$< 1.5\text{ ns}$ - Commercial Off-The-Shelf COTS Readiness : Can be deployed immediately using accessible hardware: AMD Xilinx UltraScale+ FPGA SmartNICs ~€2,800 or Intel Tofino 2 P4 Switches ~€8,500 . . ├── README.md English Documentation & Quickstart ├── README IT.md Italian Documentation & Quickstart ├── requirements.txt Optional dependencies rich, numpy, matplotlib ├── config.py Optical physical constants & simulation parameters ├── core/ │ ├── encoder.py WDM optical wavelength modulation C-Band 1530-1565nm │ ├── switch.py In-network optical switch and in-transit compute engine │ └── matrix sparse.py 1.58-bit ternary additive engine {-1, 0, 1} ├── simulation/ │ ├── fiber channel.py Single-mode silica fiber delay & attenuation model SMF-28 │ ├── pipeline.py Multi-hop end-to-end execution pipeline │ ├── heterogeneous network.py Global WAN model Copper, P4 Cabins, Fibers, LEO Satellites │ └── packet classifier.py Hardware packet classifier <1.5 ns TCAM parser ├── benchmarks/ │ ├── metrics.py FLOPs, Latency, and Energy telemetry picoJoules vs milliJoules │ ├── compare gpu.py Mathematical comparison vs NVIDIA H100 GPU server │ └── hardware costs.py 3-Year TCO financial engine CAPEX & OPEX ├── docs/ │ ├── WHITEPAPER.md Formal scientific whitepaper & mathematical models │ ├── hardware architecture.md Technical hardware guide for COTS chips & optical interconnects │ └── IMPACT AND ROADMAP.md Global launch manifesto, grants EIC Pathfinder , and roadmap ├── tests/ │ └── test all.py Automated test suite 100% passing └── main.py Interactive CLI with Rich terminal visualization Zero complex setup required. Operates using standard Python 3.10+: Run baseline simulation 3 in-network optical switches with cost & GPU comparison python3 main.py --prompt "LightSwitch routes intelligence directly into optical media" python3 main.py --global-wan --prompt "Global distributed intelligence in transit" python3 main.py --traffic-filter python3 -m unittest discover tests | Hardware Architecture | Chip Type | CAPEX Hardware | Power Consumption | 3-Year Electricity OPEX | 3-Year Total TCO | Savings vs GPU | |---|---|---|---|---|---|---| Traditional AI Server 8x NVIDIA H100 | Monolithic GPU | €280,000 | 10,200 W | €70,815 | €350,815 | Baseline | 3x FPGA SmartNIC Cluster | AMD Xilinx COTS | €8,400 | 225 W | €1,562 | €9,962 | -97% 🚀 | 3x Programmable P4 Switch Cluster | Intel Tofino 2 COTS | €25,500 | 750 W | €5,207 | €30,707 | -91% 🚀 | 3x Silicon Photonics CPO Engine | Ayar Labs COTS | €36,000 | 105 W | €729 | €36,729 | -90% 🚀 | Calculated with industrial electricity rate of €0.22/kWh and cooling PUE = 1.2. - 📖 : Mathematical formulations, Maxwell wave propagation, and theoretical derivation. Scientific Whitepaper /pisantifrancesco89/Project-LightSwitch/blob/main/docs/WHITEPAPER.md - 🛠️ : Commercial chips, QSFP28 pinouts, MZI optical meshes, and distributors. Hardware Architecture Guide /pisantifrancesco89/Project-LightSwitch/blob/main/docs/hardware architecture.md - 🌍 : Open-source strategy, European deep-tech grants EIC Pathfinder , and telecom integration. Roadmap & Manifesto /pisantifrancesco89/Project-LightSwitch/blob/main/docs/IMPACT AND ROADMAP.md Released under the open-source MIT License /pisantifrancesco89/Project-LightSwitch/blob/main/LICENSE .