{"slug": "leading-edge-ai-ic-designs-demand-comprehensive-hav-methodologies", "title": "Leading-edge AI IC designs demand comprehensive HAV methodologies", "summary": "Siemens highlights that hardware-assisted verification (HAV) methodologies, including emulation and FPGA-based prototyping, are essential for developing advanced AI chip designs, citing its Veloce CS system which combines Veloce Strato CS, Veloce Primo CS, and Veloce ProFPGA CS. The demand for faster AI processing drives the need for comprehensive verification to ensure reliability and speed to market for complex designs like a 20-billion-gate 3nm accelerator.", "body_md": "Driven by insatiable demand to enable AI to process more data faster, the design teams building today’s most advanced ICs at the heart of AI systems rely on hardware-assisted verification to develop SoCs, software that to runs on these SoC, and finally the ability to perform full system verification and validation. Emulation, the more traditional and hardware verification focused technology in HAV, facilitates the creation of models of a given IC design in register transfer level (RTL) RTL code. This executable model gives design teams full observability into the functionality of their design and allows them to debug the IC design, make necessary corrections, and ultimately verify the design functions to its specification before sending it to layout and manufacturing, where it will become an IC.\n\nA more recent HAV technology, called FPGA-based prototyping, is trading off some hardware observability of emulation for greater execution speed. Because of its 5X to 10X increased performance over emulation, an FPGA prototyping enables software teams to develop firmware and even apps and perform system validation with software running on the hardware design before the IC design is available in silicon. They can then fix the IC design to optimize software and system performance. Having the design running on hardware also enables software teams to get an early jump on application software development. Together emulation and FPGA-based prototyping are invaluable to helping companies develop more reliable products faster. This is especially important in the AI era.\n\nLet’s take a closer look at some HAV methodologies used for today’s most advanced AI designs. We draw on this experience from decades of offering HAV technologies and from Siemens’ recent release of our state-of-the-art Veloce CS system, which consists of the Veloce Strato CS emulation system, Veloce Primo CS enterprise prototyping system and Veloce ProFPGA CS FPGA-based prototyping system (Figure 1).\n\n**Insatiable demand for faster AI with greater functionality**\n\nThe size of chip designs is driven today by artificial intelligence—in training and executing generative AI models, powering smart vehicles, and general intelligence research. Leading-edge IC processes and increasingly 3D ICs feed the hunger and abet the growth of AI.\n\n[View All](https://www.eetimes.com/category/sponsored-content/)\n\nThe bulk of these huge designs are still done by companies like NVIDIA, AMD, Intel, Qualcomm, etc. – designing CPUs and GPUs for system houses such as cloud service providers, datacenters, hyperscalers and auto manufacturers.\n\nFor chip vendors, the product is the chip. If the chip conforms to its data sheet, it is correct. For a system house, the product is the system; the chip, on its board, running its entire software stack from drivers and operating systems up through applications. It is the integrated system that they must test, not just modules of the RTL.\n\nFor example: A cloud provider’s team must develop an accelerator for training generative AI models.\n\nThe design includes an accelerator ASIC – a large array of specialized vector processors and memory instances, CPU and DSP cores, and high-bandwidth I/O. The large 3nm die has the equivalent of about 20 billion gates.\n\nThis chip sits on a server board with high-speed memory, optical transceivers, and a system management CPU, controlled by a Linux kernel and furnished with AI development frameworks and a proprietary generative AI tool. The development schedule demands that RTL design of the vector processor, IP integration for the whole chip, and software development and testing all begin together and run concurrently.\n\nThis example highlights some specific needs for the systems where the RTL code and software is developed and tested. The degree to which these needs are met determines both adherence to the schedule and product success.\n\n**Time is money**\n\nAdherence to design schedules is imperative. Being first to market with a leading-edge AI IC design is crucial to an IC design company’s success and adding new AI functionality is crucial to a systems company’s success, too.\n\nHaving state-of-the-art HAV system with compatible FPGA-based prototyping and emulation enables design teams to maximize their efficiency. Moving designs back and forth between FPGA-prototyping and emulation via a common interface with congruent behavior enables teams to optimize their verification and validation methodologies (Figure 2).\n\n**HAV must offer full-design capacity but also fine granularity**\n\nToday’s AI designs can comprise tens of billions of gates. It is possible to partition the design and test each piece separately with its own isolated test bench. In fact, most designs begin IP design this way.\n\nFor IP integration and chip-level RTL verification, the necessary partitioning and test-bench design become a huge project with no guarantee that the results predict the behavior of the full design. To perform comprehensive RTL code debug of an entire IC design is no substitute for a single model of the entire design. The same stands true for the software team where there is no substitute for seeing the full code stack run on the full chip model. Because of this, emulation and prototyping systems need to be able to handle the entire RTL design.\n\nGranularity is just as important. The hardware team may begin with design exploration of a single vector processor comprising only a few 10’s of million gates. The need for system capacity can ramp up from there, as the team assembles the network of vector processors and memory instances, adds third-party IP, and begins to verify behavior of the full chip. A fully scaled-out emulation system may not be needed from the beginning. The same is true of an enterprise prototyping system for the software team. But as these designs develop, a full HAV system will be needed.\n\n**HAV performance is paramount**\n\nPerformance is non-negotiable and has two components: execution speed and compile speed. For an emulation system, execution speed determines how long a given hardware test takes. This time delay determines how many things the verification team tries as they explore the verification space. During verification, verification is only finished when the team runs out of time, execution speed determines the depth of verification coverage.\n\nBoth factors contribute to overall design quality and schedule adherence. Compile speed is important in the early part of the verification to get faster turnaround time: compile => run=> find/fix bug => compile => validate.\n\nFor the enterprise prototyping system, execution speed is essential to determine whether it is practical or possible to run full software workloads on the full RTL model.\n\nShareability is equally critical for extremely large design projects. HAV systems should be capable of supporting multiple groups scattered around the globe. They logically should reside in an enterprise datacenter, the nexus of the fastest and most secure enterprise networks. It should be easy for the systems to support multiple design efforts and easy for IT organizations to install and support them in enterprise datacenters.\n\nA final need involves how these extended design teams work. In practice, RTL design and software design teams are working in parallel interactively. When the software team’s enterprise prototyping system uncovers a bug, the software developers may huddle with the hardware team to search for the root cause using the emulation system. It is essential that the emulation and prototyping systems share the same RTL model, and that it behaves the same way on both systems. Any discontinuity in user interface, in the way commands operate, or in the representation of data between the two systems adds delay and the potential for errors.\n\nGiven the importance and difficulty of these needs, it is worth an enterprises’ time to examine which HAV vendor offers the most comprehensive system that can also scale to the growing demands of the I market. Siemens EDA offers a complete and the industry’s most modern and integrated HAV flow with the Veloce CS suite. For more information, please read the white paper, “[Meeting the challenge of concurrent RTL and workload verification and validation](https://resources.sw.siemens.com/en-US/white-paper-meeting-the-challenge-of-concurrent-rtl-workload-verification-and-validation/?utm_campaign=2026-3-global-eda_awareness&utm_source=ee_times&utm_medium=content_network&utm_content=hav&cmpid=119507).”", "url": "https://wpnews.pro/news/leading-edge-ai-ic-designs-demand-comprehensive-hav-methodologies", "canonical_source": "https://www.eetimes.com/leading-edge-ai-ic-designs-demand-comprehensive-hav-methodologies/", "published_at": "2026-08-10 13:00:00+00:00", "updated_at": "2026-08-10 13:17:28.100595+00:00", "lang": "en", "topics": ["ai-infrastructure", "ai-chips"], "entities": ["Siemens", "Veloce CS", "Veloce Strato CS", "Veloce Primo CS", "Veloce ProFPGA CS", "NVIDIA", "AMD", "Intel"], "alternates": {"html": "https://wpnews.pro/news/leading-edge-ai-ic-designs-demand-comprehensive-hav-methodologies", "markdown": "https://wpnews.pro/news/leading-edge-ai-ic-designs-demand-comprehensive-hav-methodologies.md", "text": "https://wpnews.pro/news/leading-edge-ai-ic-designs-demand-comprehensive-hav-methodologies.txt", "jsonld": "https://wpnews.pro/news/leading-edge-ai-ic-designs-demand-comprehensive-hav-methodologies.jsonld"}}