Lamb Labs, founded by Niki Kotecha and Thomas Lanning, said in a thread on X on August 4th that its planned custom inference chips could generate more than 20,000 tokens per second and deliver 63 times the "Intelligence per Watt" of traditional GPUs.
https://x.com/LambLabs/status/2084692794388418746 Those figures are Lamb Labs targets, rather than independently tested results. Lamb Labs has not published the model, batch size, precision, latency methodology or GPU baseline behind the comparison. It has also not detailed the chip architecture, fabrication process or production schedule required to reproduce the result.
The benchmark claims sharpen the hardware thesis that Kotecha and Lanning outlined when they brought Lamb Labs out of stealth in July. Lamb Labs is part of Y Combinator's Summer 2026 batch and is designing chips for local inference in robots, humanoids, phones, wearables and industrial equipment. The stated goal is to run capable models without a cloud connection or datacenter-scale power budget.
Kotecha arrived at the chip project through AI research rather than semiconductor manufacturing. She earned BA and MEng degrees in chemical engineering from the University of Cambridge before pursuing a PhD at Imperial College London. Her work applied multi-agent reinforcement learning and graph neural networks to decentralized supply-chain decisions, including research on inventory control. She previously founded Transpexa, which used related methods for inventory, logistics and demand forecasting, according to an Imperial College profile.
Lanning's public profile says he announced plans to work as a student researcher at Google DeepMind. More recently, his updates have documented Lamb Labs' FPGA experiments, including a 7-billion-parameter model drawing about six watts and a quantized 27-billion-parameter model that fit on the same class of development board but ran slowly.
That prototype work shows the gap Lamb Labs still has to close. A Y Combinator post reproduced on Lamb Labs' LinkedIn page says the current 8-billion-parameter FPGA prototype operates below 10 watts. Lamb Labs is targeting deployments below one watt, a substantially tighter power envelope for battery-operated devices.
Y Combinator said Lamb Labs' approach combines model-specific hardware, aggressive quantization and diffusion-based inference. The accelerator described the long-term thesis as giving each AI model its own custom silicon. That would trade some of the flexibility of general-purpose GPUs for hardware tuned around a narrower model and workload.
Lamb Labs calls its central metric Intelligence per Watt, or IPW. That framing attempts to account for model capability as well as speed and electricity use, but Lamb Labs has not published the formula used to score intelligence. Without a defined evaluation and common hardware baseline, the 63x figure cannot be compared with conventional performance-per-watt measurements.
The market for specialized inference processors already spans datacenter systems and low-power devices. Groq built its LPU around deterministic execution and on-chip memory, while Cerebras sells high-speed inference on wafer-scale systems. Hailo targets edge equipment with lower-power AI accelerators. Lamb Labs is making a narrower wager around model-specific chips and power budgets small enough for embedded generative AI.
Lamb Labs' place in YC gives Kotecha and Lanning initial financing while they work through that hardware cycle. YC's standard deal invests $500,000 through two safes: $125,000 for 7% and $375,000 on an uncapped most-favored-nation safe.
A taped-out chip running a named model under specified conditions will determine whether Lamb Labs' figures describe a product or a design objective. The FPGA results establish that Kotecha and Lanning are running quantized language models on programmable hardware. Reproducible speed, model quality and wall-power measurements remain the proof required for the 20,000-token and 63x claims.