Kepler Compute- New memory startup for AI

Kepler Compute, a new memory startup, announced it is developing leadership memory beyond HBM and SRAM that it says can be built without dependence on EUV lithography, with sampling planned for 2026 and production in 2027. The company states its Kepler memory is designed to approach the bandwidth per watt of SRAM while exceeding the capacities of SRAM and HBM, targeting next-generation inference, and that it is working through 2028-30 allocations. Kepler's founding team includes co-founders and executives who previously worked on Intel's Foveros 3D stacking, seven generations of DRAM, first-to-market 232-layer NAND, and ferroelectrics research.

01 Leadership chips without EUV It is possible to build leadership chips without a dependence on EUV Leadership memory beyond HBM & SRAM. Sampling in 2026. Production in 2027. A new frontier of bandwidth, capacity and energy Our team lives and breathes computing across the stack and has created many industry firsts.We have led the development and scaling of technologies to billions of chips across mainstream transistors, 3D logic stacking, seven generations of DRAM, first to market 232-layer NAND, and mobile SoCs. We built the world's first commercial physical synthesis tool, developed foundational EDA techniques across the industry and have solved long-standing challenges in ferroelectrics and beyond-CMOS devices and memories. WHAT WE BELIEVE 02 It is possible to achieve multiple orders of magnitude more intelligence per watt by evolving chips 2D Silicon to 3D Beyond silicon 03 It is possible to get much closer to the physical limits of computing than we are today while staying within mainstream digital computing WHAT WE OFFER Kepler memory is designed to approach bandwidth per watt of SRAM and go beyond the capacities of SRAM and HBM. Enabling a new frontier of throughput and interactivity for next generation inference SILICON TO VOLUME We are working through 2028-30 allocations. Co-founder & CTO Founded Intel’s FEINMAN center for next generation logic and co-invented MESO - a candidate spin based Beyond CMOS logic device. Demonstrated First 50 Gb/s silicon micro ring modulator. CO-FOUNDER, CTO, DESIGN & HARDWARE. CHIEF ENGINEERING OFFICER Co-led definition on Intel Foveros 3D stacking, built high speed circuits that have enabled high volume cpu products Co-founder & CTO, Software & Architecture Created and scaled CosmoFlow and built computational-lithography software used in Intel’s 14nm process. Co-founder & Chief Science Officer Solved long standing problems like fatigue in ferroelectrics, discovered new multiferroic devices for low energy computing Co-founder & CEO Co-founded Gigster. Demonstrated stimulated emission in work to build a silicon laser during Cornell Physics PhD. Theoretical physics of domain wall motion in spintronics MEMORY BU Scaled seven generations of DRAM to millions of wafers and helped bring first-to-market 232-layer NAND into volume manufacturing. PROCESS INTEGRATION First FInFET integration of SRAM replacement ferroelectrics and led 6 month ramp of a new dedicated 300mm fab from a cold start to electrical data ADVANCED PACKAGING Key contributor to world's first FinFET technology awarded the Intel Achievement award . Lead inventor for Intel's precision resistor technology used in high volume manufacturing. MODULES Led the development and integration of the world's first 300mm magnetic memory and logic platform. PRODUCT & IP Built world's first commercial physical synthesis tools that helped establish Synopsys as a leader, from synthesis through automatic layout. Won the 2019 Robert Noyce Medal. MANUFACTURING LEADERSHIP· sram · DRAM · logic Kepler uses the physics of 3D and new materials to produce leadership logic and memory systems that leapfrog EUV only approaches. Allowing for more intelligence per fab and more fabs per dollar Memory first. Then replace the transistor. REACH OUT For customers, partners, press and people who want to join the team.