Intel Runs 816B Muse Spark Open on 4 GPUs [2026]

Intel published Day-0 support for Meta's Muse Spark Open, an 816 billion-parameter any-to-text model Meta released as open weights on October 15, 2026, running it across four upcoming Intel GPU D-series cards with 160 GB of LPDDR5x memory each. Intel's newsroom page, updated November 5, 2026, states the model uses 42B active parameters per token in a sparse mixture-of-experts design with a 1,048,576-token context window, and that Intel enabled the support through low-bit model quantization on Xeon processors and data center GPUs. The page lists no price, ship date, benchmark or spokesperson quote, and the D-series hardware is not yet on sale.

Intel says it has Day-0 support for Meta’s Muse Spark Open https://www.intel.com/content/www/us/en/newsroom/news/artificial-intelligence/intel-offers-day-0-support-for-meta-muse-spark-open.html , the 816 billion-parameter any-to-text model Meta released as open weights on October 15, 2026. The company’s newsroom page went live that day and was updated on November 5, 2026, which is why the story is back in front of hardware readers this week. The headline hardware detail is a GPU that Intel has not shipped yet: an upcoming Intel GPU D-series card with 160 GB of memory, running the model across four cards. That pairing matters because Muse Spark Open is huge on paper and lean at runtime. Intel and Meta both describe 816B total parameters with 42B active per token, wrapped in a sparse mixture-of-experts design with a roughly 1M-token context window. We covered the model’s rivals in our Muse Spark Open vs DeepSeek V4.1 vs Beam context comparison https://shattered.io/muse-spark-open-vs-deepseek-v4-1-flash-vs-beam-1-0-1m-context-2026/ . This piece looks at the other half of the story: which silicon can actually hold the thing. A caution before the details. Intel’s page gives capacity and platform facts, but the sources we reviewed list no price, no ship date, no benchmark and no named spokesperson quote. Outlets including Igor’sLAB and DQ have repeated the Intel announcement, and none of that coverage adds measured performance. We separate what is confirmed from what is inference throughout, and we label our own arithmetic as ours. Don't miss new tech stories on Google Add Shattered once in the Google app and our stories show up in your news suggestions. Add now https://www.google.com/preferences/source?hl=en&q=https%3A%2F%2Fshattered.io%2F What Intel Actually Announced Intel’s announcement makes four claims. First, it enabled Day-0 support for Muse Spark Open across Intel Xeon processors and its data center GPU platforms, specifically the Intel GPU D-series. Second, it did that using low-bit model quantization. Third, it has tested the model and has it running on the upcoming D-series. Fourth, each GPU carries 160 GB of memory, and that is enough to run the model across four GPUs. Intel also separated the Xeon news from the GPU news. The company announced Day-0 support for Muse Spark Open on Xeon processors as its own item, which tells buyers that the CPU path is meant as a real deployment option and not a footnote. The memory configuration listed for the D-series is 160 GB of LPDDR5x, with options up to 480 GB. Day-0 support has a specific meaning in this industry. It means the vendor’s software stack could load and run the model on launch day, so developers did not wait weeks for kernels and quantized checkpoints. It does not mean the vendor published speeds, and it does not mean the hardware is on sale. Intel’s wording fits that narrower definition. The GPU is described as upcoming, and the page offers no customer availability date. The date detail also deserves care. The page’s original publication date is October 15, the same day as Meta’s release, and the November 5 update is what put it back on the radar. We have no changelog showing what changed in the update, so we do not claim new content. We report the page as it stands today. The Muse Spark Open Specs Behind the Support Meta’s own Muse Spark Open model page https://dev.meta.ai/docs/muse-spark-open confirms the core numbers. The model carries 816B total parameters and 42B active parameters, uses a sparse mixture-of-experts architecture, and is multimodal. It accepts text, image, audio and video input and produces text output. The context window is 1,048,576 tokens, which Meta also calls a 1M-token context window. SiliconANGLE’s report on the release framed the model around coding and agent work https://siliconangle.com/2026/10/15/meta-releases-816b-parameter-muse-spark-open-for-coding-and-agent-work/ , which lines up with the long context window. Agent loops stuff tool outputs, file contents and prior turns into the prompt, so a 1M-token window is a practical feature and not a marketing number. It is also the feature that stresses memory hardest, a point we return to below. | Item | Confirmed value | Source | |---|---|---| | Total parameters | 816 billion | Intel, Meta model page | | Active parameters | 42 billion | Meta model page | | Architecture | Sparse mixture of experts, multimodal | Meta model page | | Input | Text, image, audio, video | Meta model page | | Output | Text | Meta model page | | Context window | 1,048,576 tokens about 1M | Meta model page | | Release date | October 15, 2026 | Intel newsroom, SiliconANGLE | For a wider look at how this release sits next to other open models, see our open-weight AI models spec sheet https://shattered.io/open-weight-ai-models-side-by-side-the-spec-sheet/ . The short version is that few open releases combine this parameter count with a context window this long, and that combination is what pushes the hardware question from “can it run” to “what does it cost to hold”. Why 816B Total and 42B Active Changes the Hardware Math Mixture-of-experts models split the work in a way that confuses first-time buyers. Only 42B parameters fire for each token, so the compute per token looks like a mid-sized dense model. But the router can pick any expert on the next token, so all 816B parameters must stay resident in fast memory. Compute shrinks, and memory capacity does not. That asymmetry explains why Intel led with memory in its announcement. A card with enormous raw math but modest memory cannot host this model without splitting it across many devices, which adds interconnect traffic and cost. A card with a large pool of cheaper memory can hold more of the model per device. Intel chose the second path with 160 GB of LPDDR5x per GPU, according to its own page. The trade-off is bandwidth. LPDDR5x is generally slower than the stacked HBM memory used on flagship accelerators, and token generation is usually limited by how fast weights stream from memory. Intel’s page, as we reviewed it, lists capacity but no bandwidth figure. Until that number appears, any claim about tokens per second on the D-series is a guess, and we decline to make one. The sparse design helps here. Because only 42B parameters are active, the data that must move per token is a fraction of the full model, so a bandwidth-limited card suffers less than it would on an 816B dense network. That is the strongest argument for the D-series approach, and it is the reason capacity-heavy designs suit mixture-of-experts models better than they suit dense ones. Xeon Gets Day-0 Support: The CPU Route The Xeon announcement is easy to skip, and it shouldn’t be. Server CPUs sit in nearly every data center already, and they can address far more system memory than any single accelerator. Running a sparse model on CPUs trades speed for capacity and for the ability to reuse existing racks. Intel says it enabled this on day one, using low-bit quantization to shrink the weights. Who benefits? Teams that want to test an 816B model without queuing for scarce accelerators. A developer who needs to check output quality on private data, run an overnight batch job, or prototype an agent flow can tolerate slower generation. A product serving thousands of live users cannot. We have no Intel throughput figures for Xeon either, so we cannot say where that line falls. The CPU path also hedges Intel’s own risk. The D-series is upcoming, which means the only Intel silicon a customer can buy today to run the model is Xeon. Announcing both paths together lets Intel claim coverage across its data center line without waiting for the GPU to ship. The Intel GPU D-Series: 160 GB Per Card, Four Cards The D-series is the part of the announcement that carries hardware news. Intel says the upcoming Intel GPU D-series runs Muse Spark Open today in testing, with 160 GB of memory on each GPU and a four-GPU configuration large enough for the model. That is the full extent of the confirmed capability claim. How the Four-Card Memory Math Works Four cards at 160 GB each give 640 GB of pooled capacity. That total is our arithmetic and not an Intel-published figure, and it assumes the four cards share the model evenly. The table below shows how weight storage scales with precision. These are back-of-envelope numbers for the weights alone, and they ignore the key-value cache, activations and runtime overhead. | Weight precision | Bytes per parameter | Approx. weights for 816B | Fits in 640 GB weights only ? | |---|---|---|---| | 16-bit BF16 | 2 | 1,632 GB | No | | 8-bit | 1 | 816 GB | No | | 6-bit | 0.75 | 612 GB | Barely, little room for cache | | 4-bit | 0.5 | 408 GB | Yes, about 232 GB left over | The table explains Intel’s phrasing. Intel says four GPUs are sufficient with low-bit quantization, and the arithmetic backs that up. At 8-bit the weights alone overflow four cards. At roughly 4-bit they fit with a few hundred gigabytes to spare. Quantization is not a nice extra here. It is the condition that makes the four-card claim work. What Intel Has Not Said Intel has not published the interconnect between the cards, the memory bandwidth, the power draw or the launch window in the material we reviewed. It has not given a price. It has not stated how much the leftover memory supports in terms of context length, which matters because a full 1M-token window can consume a large cache. A buyer cannot size a deployment from the current facts. A buyer can only conclude that the card is designed with this class of model in mind. Low-Bit Quantization: The Trade Intel Is Making Both of Intel’s platforms rely on low-bit quantization, so quality loss is the question every evaluator should ask. Compressing 16-bit weights down to around 4 bits cuts memory by about three quarters, and it can nudge accuracy downward, especially on reasoning, code and long-context recall. The size of that drop depends on the method and on the model. The sources we reviewed publish no accuracy comparison between Intel’s quantized builds and the full-precision model. That gap should shape procurement. Any team planning to serve the model on Intel hardware needs to run its own evaluation set against the quantized checkpoint, since public leaderboards will mostly reflect the original weights. A coding agent that fails one test in twenty more often is a different product from the one Meta demoed. Sparse models raise a second wrinkle. Rarely used experts may tolerate coarse quantization differently from the shared layers, and tooling that treats them all the same can hurt quality in uneven ways. Vendors usually hide those details behind a single “supported” label. Day-0 support tells you the model loads and answers. It does not tell you the answers match the original. How Intel Compares With Nvidia, AMD and Apple Intel is not alone. Meta’s model page lists inference engines including SGLang, vLLM, TensorRT-LLM, Hugging Face Transformers, Apple MLX, llama.cpp and Unsloth, with optimizations for AMD, Apple, Intel and NVIDIA silicon. So every major vendor has a launch-day story, and Intel’s distinction is the specific memory-per-card pitch and the CPU route. Apple has its own angle. Mashable reported that Meta and Apple teamed up to bring the 800B-class open-weight model to Mac Studio, as part of an Apple and Meta collaboration https://me.mashable.com/tech/77292/meta-and-apple-team-up-to-bring-800b-open-weight-muse-spark-open-ai-to-mac-studio that targets desktop-class unified memory. That is a different buyer from Intel’s data center customer, but it shows the same idea. Whoever holds the most memory per dollar wins the open-model hosting argument. | Vendor | Muse Spark Open status | What is confirmed | What is missing | |---|---|---|---| | Intel Xeon | Day-0 support announced | Low-bit quantization path | Speed figures | | Intel GPU D-series | Running in testing, hardware upcoming | 160 GB per GPU, four GPUs suffice, options up to 480 GB | Price, date, bandwidth, benchmarks | | Apple | Mac Studio route reported | Meta and Apple collaboration per Mashable | Our sources give no throughput data | | Nvidia and AMD | Optimizations listed by Meta | Named in Meta’s verification list | Specific card claims in our sources | CPU competition is heating up as well. Our earlier report on Nvidia’s Vera CPU claim against AMD’s EPYC Venice rebuttal https://shattered.io/nvidia-vera-cpu-1-8x-claim-vs-amd-2-24x-epyc-venice-2026/ shows server CPUs are now fighting for AI inference work too, and Intel’s Xeon pitch for Muse Spark Open fits that trend. Market Impact: Memory Capacity Is the Selling Point The AI hardware market spent two years arguing about compute. Open models with hundreds of billions of parameters are shifting the argument toward capacity. When a model needs 400 GB or more just to sit in memory, the buyer’s first question becomes how many cards it takes, and the answer drives cost per deployment more than peak FLOPS do. Memory supply is tight, which complicates Intel’s pitch. Our report that Samsung sold out its 2027 HBM https://shattered.io/samsung-sells-out-2027-hbm-as-hbm4-sales-triple-supply-crunch-2026/ shows how scarce high-bandwidth memory has become. A design that leans on LPDDR5x, a commodity-style memory, sidesteps part of that squeeze. That is a plausible strategic reason for Intel’s design, though Intel’s page does not state it, so treat it as our reading. Pricing pressure elsewhere in the memory market is a risk as well. We covered Apple’s warning about unprecedented RAM costs https://shattered.io/ternus-warns-ram-costs-unprecedented-two-price-moves-developers-2026/ , and the same pressure could hit a card with 160 GB, or up to 480 GB, of LPDDR5x. Intel gave no price, so nobody can say yet whether the capacity advantage survives rising memory costs. For Intel, the announcement is also a credibility play. The company needs customers to believe its next accelerator is real, and showing a flagship open model on it, in testing, is cheaper than shipping silicon. It is a signal, and signals are only as good as the products that follow. Historical Context: Open Weights Meet Hardware Bets Meta’s Llama line made open-weight releases a fixture of the AI calendar, and chipmakers learned to publish same-day support notes to claim a share of the attention. Intel has played this game before, including with its Gaudi accelerators, and has had a harder time converting software support into hardware share than Nvidia has. That history is why analysts will read the D-series pitch skeptically until independent numbers appear. The scale has changed, though. Earlier open releases fit on a handful of high-end GPUs or even a workstation. An 816B-parameter model with a 1M-token window forces a different class of machine. That shift opens a door for vendors who can offer cheap capacity, and Intel is trying to walk through it. Intel’s manufacturing roadmap sits behind all this. Our coverage of the Intel 14A PDK 0.9 release https://shattered.io/intel-14a-pdk-0-9-available-pdk-1-0-q1-2027-2026/ shows the company still pursuing process leadership while it rebuilds its AI product line. A competitive accelerator and a competitive foundry are separate bets, and Intel needs both to pay off. The Software Stack Behind Day-0 Day-0 support is mostly a software achievement. Meta’s list of engines shows how fragmented deployment has become: SGLang and vLLM for serving, TensorRT-LLM for Nvidia, Transformers for research, MLX for Apple, llama.cpp for local and CPU use, and Unsloth for fine-tuning. A vendor that wants launch-day relevance must get its kernels and quantization into those projects before the weights drop. Intel’s quantization approach gave it a path into that ecosystem. Low-bit checkpoints let the same model run on a CPU or a GPU with very different memory budgets. The unanswered question is how much of Intel’s work lands upstream in open projects versus staying in Intel-specific tooling, which determines how easily a customer can switch away later. Developers should also watch release cadence. A model that gets patched weekly can break a quantized checkpoint, and vendors differ in how fast they respond. Day-0 is a starting line, and the real test is whether support keeps pace at day 30. What Developers and IT Buyers Should Do Now Start with the memory budget, not the logo. Decide which precision your workload tolerates, then compute the weight footprint plus cache for your longest realistic prompts. Our table above gives the weight side, and your own evaluation gives the quality side. This sizing step takes an afternoon and prevents a six-figure mistake. Next, test on hardware you can get today. Xeon-based servers can run the quantized model now, according to Intel, and a pilot there will reveal quality and latency limits before any D-series card exists. Pair it with a cloud or Mac-based trial so you have a comparison point. Finally, hold purchase decisions until Intel publishes price, bandwidth and a ship window. Buying on a Day-0 announcement alone means buying on a promise. For a broader view of data center silicon trends, browse our hardware coverage https://shattered.io/hardware/ . What Remains Unconfirmed Several claims circulating around this story lack support. The phrase “built for 816B scale” is a headline paraphrase and not an official Intel product designation. The confirmed figure is the model’s 816B total parameters. No specific Intel price, customer availability date, benchmark result or performance claim appears in the records we reviewed. No named Intel or Meta spokesperson quote appears either. We also found no independent test of the D-series. Everything about the card’s behavior comes from Intel itself, which has an interest in presenting it well. Treat the four-GPU claim as a vendor statement until a third party reproduces it. Five Predictions for Intel and Open-Model Hardware These are our forecasts, not reported facts. - Intel will publish throughput numbers within months. A Day-0 claim without speeds can’t hold buyer attention for long, and competitors will fill the silence with their own comparisons. - Quantization quality will become the main fight. Expect third-party tests of 4-bit builds against full-precision weights, and expect results to vary by task. - Memory capacity will appear in more accelerator marketing. Rivals with HBM will stress bandwidth, and capacity-first designs will stress cost per hosted model. - CPU inference for sparse models will stay a niche. It will serve testing and batch work, not high-traffic serving. - Day-0 support announcements will multiply. As open models grow past 800B parameters, every vendor will publish one, and buyers will learn to discount them without measured data. FAQ What did Intel announce for Muse Spark Open? Intel announced Day-0 support for Meta’s Muse Spark Open across Xeon processors and its data center GPU platforms, including the upcoming Intel GPU D-series. The page was published on October 15, 2026 and updated on November 5, 2026. How big is Muse Spark Open? Meta lists 816B total parameters and 42B active parameters in a sparse mixture-of-experts design. It accepts text, image, audio and video and outputs text, with a 1,048,576-token context window. How much memory does each Intel D-series GPU have? Intel states 160 GB per GPU, and it lists 160 GB of LPDDR5x with options up to 480 GB. Four GPUs are enough to run the model with low-bit quantization, according to Intel. Can I buy the Intel GPU D-series today? No. Intel calls it upcoming, and the sources we reviewed give no price or availability date. Is there a benchmark for Muse Spark Open on Intel hardware? Not in the records we reviewed. Intel reports that the model runs in testing, but it published no speed or accuracy numbers. Which other chipmakers support the model? Meta’s model page lists optimizations for AMD, Apple, Intel and NVIDIA silicon, and Mashable reported a Meta and Apple effort for Mac Studio. Why does low-bit quantization matter here? It shrinks the weights enough to fit. By our arithmetic, 816B parameters at 8-bit need about 816 GB, which overflows four 160 GB cards, while 4-bit needs about 408 GB and fits.