Intel Details Xeon 7 "Diamond Rapids" Package Design at HOT CHIPS

Intel detailed the package design of its next-generation Xeon 7 "Diamond Rapids" server processor at HOT CHIPS, targeting enterprise-scale agentic AI with up to 256 P-cores and 1.28 GB of last-level cache per socket. The processor uses a disaggregated multi-chip module with two Fabric Hub Tiles, four CPU core Base Tiles, and 16 core chiplets, each with 16 "Panther Cove" P-cores, built on Intel's 18A-P process node.

Intel, in a detailed presentation, detailed the package design of its next-generation Xeon 7 "Diamond Rapids" server processor. The processor is designed to be a versatile serial processing powerhouse for enterprise-scale agentic AI. Intel's design goal with the processor is to offer up to 256 P-cores, cushioned by up to 1.28 GB of last-level cache, per socket. The chip also features contemporary I/O, including PCI-Express Gen 6. Intel is leveraging its latest in-house foundry node, the Intel 18A-P, to design the core complex chiplets. Xeon 7 "Diamond Rapids" is built on essentially the same disaggregation philosophy as AMD EPYC—that of CPU cores being spun out in small groups of CPU core complexes CCXs contained in CPU core dies CCDs , groups of which interface with a centralized server I/O die sIOD , which serves as a system agent and I/O hub. The "Diamond Rapids" MCM consists of two Fabric Hub Tiles FHTs , four CPU core Base Tiles, and a total of 16 core chiplets, each containing 16 "Panther Cove" P-cores. The core-count per compute base tile is 64, and four of these add up to 256 cores.