Intel opened Hot Chips 2026 by laying out Crescent Island, a data center GPU purpose-built for agentic AI inference. Chief Enterprise AI Systems architect Sumit Mohan and Intel Fellow Hong Jiang walked through a design centered on tokens per watt, large memory capacity, and an open software stack. We covered Intel’s AI roadmap at its Computex 2026 keynote earlier this summer, and this talk fills in the accelerator that sits at the top of that portfolio.
This session is being written live, so please excuse any typos.
Intel Crescent Island at Hot Chips 2026 #
Agentic AI shifts the pressure points compared with plain chatbots. Intel frames the problem in terms of latency, memory capacity, and system throughput, since tool calls, long context, and CPU-GPU coordination all tax the platform at once.
Placing Crescent Island in Intel’s broader accelerator portfolio makes clear it is the enterprise data center play. Across local agent computers, AI workstations, and data center intelligence centers, Intel spreads everything from Arc Pro GPUs and SambaNova SN50 RDUs up to this new inference GPU.
Here is Intel’s roadmap timeline, which runs from 2020 into 2026 and beyond, showing that Crescent Island is not a first-generation architecture but rather part of a lineage dating back 6+ years.
Crescent Island is a 350W, air-cooled PCIe GPU built around tokens per watt. Intel says the branded card ships with 160GB of LPDDR5x memory, while the design allows partners to build ODM cards with flexible options up to 480GB, covering data types from FP4 and MXFP4 up to FP64.
Intel describes this as the third generation of its Xe Matrix Extensions. These XMX engines add a 3-way extended Xe matrix with FP4 precision co-issue and FP64 support, built on a 16-deep systolic array and optimized from the engine up to the core for efficiency.
This top-level die shows 32 Xe cores feeding 256 XMX engines. All the surrounding memory and fabric work exists to keep those units busy.
Crescent Island is Xe3p, and the generation table shows how far the design has come from Battlemage. Where Xe2 delivered 20 Xe cores and a 4-deep systolic XMX, Crescent Island brings 32 Xe cores, a 16-deep systolic array, a 1MB GRF and 512KB L1 per Xe core, a 32MB unified L2, and up to 480GB of LPDDR5x.
This SoC diagram shows the memory and data movement. A 32-core Xe block sits with a 32MB unified L2, a media engine with four decoders and four encoders, and KV-cache capacity for long-context and compressed-domain concurrent sessions, all connected via PCIe Gen5 x16 scale-up over an open switch fabric. Notably, Intel has at least three generations (maybe more?) of head-node Xeon server CPUs that you can use for PCIe Gen5 servers.
Intel lists an active idle power of 50W or less in the G0 state and a low-power idle around 10W in G8, using configurable distributed power, packet-based NoC routers with aggressive clock gating, and separate rails so GT and media DVFS stay independent.
For a data center part, RAS matters as much as throughput. NVIDIA’s Vera Rubin NVL72 Rack at Hot Chips 2026 talk was focused a lot on the reliability portion. Crescent Island brings ECC and parity across key memory, error checking on every hop of the internal IP fabric, dynamic page offlining, hard post-package repair, and PCIe Advanced Error Reporting, which Intel says cuts silent data corruption. Intel frames Crescent Island as designed for tokens per watt and agentic AI. On the silicon side, that means high memory capacity, KV-cache-aware routing, and prefill optimization. On the software side, Intel points to support for vLLM, SGLang, llm-d, and NVIDIA Dynamo so agents run across heterogeneous infrastructure without code changes.
More memory capacity translates directly into more usable sessions. Intel contrasts 160GB with a 96GB GPU (NVIDIA RTX Pro 6000 Server?), arguing that Crescent Island can hold FP8 weights and KV cache on a single card, enabling longer context and larger models with fewer GPUs.
This capacity chart makes a sharp point about agentic inference. Weights held grew about 7x from Llama 2 70B to Kimi K2 1T while bytes read per token fell about 4x, and Intel argues capacity and bandwidth have decoupled, which is exactly where LPDDR5x density and PCIe Gen5 switch scale-up can play.
Decode turns into a compute problem for these models. Measured across frontier mixture-of-experts designs, Intel shows 2.9 to 4.9 tokens retired per verification pass with an 8-token draft tree, arguing that the compute autoregressive decode leaves idle can be put to work with speculative decoding.
Crescent Island leans on an open development stack that Intel says hundreds of ISVs already trust, with day-0 drivers, firmware, and reference systems, so the GPU feels familiar within existing frameworks. Back when AMD won the Microsoft MI300 deal, Intel probably had a better GPU compute software stack, but obviously a lot of money is going into AMD’s stack at this point.
Beneath that layer is a concrete software stack. Intel names Triton, SYCL-TLA, oneCCL, oneDNN, SYCL, and Level Zero with an OpenCL compute runtime as the pieces. It says let the GPU inherit the broader Xe software ecosystem.
Here is the Crescent Island summary slide.
This was great stuff by Intel. Still, how much memory bandwidth does this have? I wish Intel went into more detail. If this is a 2026 part, then with a few months left, why not just show the details since it is not like another vendor (AMD or NVIDIA) is going to see the Hot Chips presentation and try to get ahead.
Final Words #
Crescent Island represents Intel’s clearest push into AI inference at the data center, and the emphasis on LPDDR5x capacity and open software gives it a different shape from competing accelerators. Whether the 350W air-cooled PCIe part can win sockets will come down to software maturity and real tokens-per-watt results, which we hope to see tested once hardware ships. How much do I want to throw these in a server, find an air-cooled variant, or heck, imagine a 480GB air-cooled variant for workstations? I guess the big question is how much memory bandwidth does this have? 650-700GB/s? More? The AMD Instinct MI350P is like 3.6-4TB/s, and the NVIDIA RTX Pro 6000 Blackwell is 1.6-1.79TB/s, IIRC, so I guess the question is also capacity. Perhaps the message is that this is actually an alternative to using LPDDR5X on the AMD Ryzen AI Halo or NVIDIA DGX Spark/ GB10? It seems like this is more of a disaggregated serving solution because Intel is funneling workload to SambaNova. Many questions still, but a neat look.
OK I am done for the day! My fingers hurt. See you all tomorrow.