Intel Coral Rapids GCC Patches Reveal a Post-Quantum ML-DSA Instruction, but No AVX10.3

Intel engineers posted GCC patches adding Coral Rapids and Razor Lake targets, with Coral Rapids introducing the AVX10_VPMLDSABFLYDQ instruction for packed ML-DSA butterfly operations, the lattice-based signature scheme NIST standardized as FIPS 204. The patches, timed for GCC 17.1 in early 2027, confirm Coral Rapids at AVX10.2 with no AVX10.3 or ACE v2, and give Razor Lake the same ISA feature set as Nova Lake; neither chip is expected before 2028. The ML-DSA instruction signals Intel expects server workloads such as TLS handshakes, code signing and certificate checks to move to post-quantum signatures, which are larger and costlier to process than elliptic-curve ones.

Intel has posted GCC enablement for its 2028-bound Coral Rapids Xeons and Razor Lake client CPUs, and the server chip brings one genuinely new instruction: hardware help for ML-DSA, the NIST post-quantum signature scheme. Intel has a habit of landing compiler support years before the silicon, and it has done it again. As spotted by Phoronix https://www.phoronix.com/news/Intel-GCC-Coral-Rapids-Razor , Intel engineers today posted patches that add Coral Rapids and Razor Lake targets to GCC. The timing lines up with GCC 17.1, due in early 2027, so the support should already be sitting in distribution compilers by the time either chip ships. Neither is expected before 2028. Razor Lake: Nova Lake, again Razor Lake follows Nova Lake on the client side, and its patch holds no surprises. It gives Razor Lake exactly the same ISA feature set as Nova Lake, whose support arrived in GCC 16. Intel has also added Razor Lake to its ISA reference https://videocardz.com/newz/intel-adds-razor-lake-desktop-and-laptop-cpus-to-its-isa-reference , and the desktop part is reportedly https://www.techpowerup.com/354565/intel-razor-lake-s-reportedly-due-in-2028-on-lga-1954 headed for the LGA-1954 socket. An unchanged instruction set is not exciting, but it does mean code tuned for Nova Lake carries straight over. Coral Rapids: one new trick Coral Rapids, the Xeon generation after Diamond Rapids, is the more interesting patch. Its feature list reads like a tour of Intel’s recent extensions: AVX10.2, APX, AMX with FP8, TF32, AVX-512 interop and MOVRS, plus SHA512, SM3 and SM4. Most of that was already confirmed for Diamond Rapids, which has had GCC support since late 2024 and is due in 2027. The newcomer is AVX10 VPMLDSABFLYDQ, a mouthful that stands for packed ML-DSA butterfly operations, and a separate patch adds the matching intrinsics. ML-DSA is the lattice-based signature algorithm NIST standardized as FIPS 204. Like other lattice schemes, it spends much of its time in the number-theoretic transform, and the butterfly is that transform’s inner step. Turning it into a single vector instruction tells you where Intel expects server workloads to go: TLS handshakes, code signing and certificate checks moving to post-quantum signatures that are larger and more expensive to process than today’s elliptic-curve ones. It is a sensible bet. Post-quantum signatures are moving into real deployments; we have covered rustls switching on ML-DSA certificates by default https://hwbusters.com/news/rustls-turns-on-post-quantum-ml-dsa-certificates-by-default-and-the-web-pki-still-cant-use-them/ and Cloudflare becoming a post-quantum certificate authority https://hwbusters.com/news/cloudflare-becomes-a-post-quantum-certificate-authority-betting-on-merkle-tree-certificates-to-keep-tls-lean/ this autumn. A server terminating millions of connections a day will feel the extra arithmetic, and a dedicated instruction is the cheapest way to hide it. Still AVX10.2, not AVX10.3 What is missing is just as telling. Earlier this week Intel and AMD published the ACE v2 and AVX10.3 specifications https://hwbusters.com/news/intel-and-amd-publish-ace-v2-and-avx10-3-bringing-4-bit-ai-formats-to-x86-years-before-the-hardware/ , yet the patch confirms Coral Rapids at AVX10.2, with no ACE v2 either. Phoronix’s read is that the design was simply too far along by the time the new specs settled. Intel also refreshed its separate GCC patch series for AVX10.3 today, now including the AVX10 BMM pieces that were missing from the first version. So the server roadmap now looks like this: Diamond Rapids in 2027, Coral Rapids in 2028 with much the same feature set plus a post-quantum accelerator, and AVX10.3 hardware further out still. None of it is close. But when it arrives, the compiler will already be waiting for it.