# Inside TSMC’s Evolving Design Ecosystem: Shaping the Future of AI, with AI > Source: > Published: 2026-09-24 14:10:55+00:00 ## *TSMC is introducing AI Design Kit to enable the future of AI-driven workflows*   In this conversation, Aveek Sarkar, director of the ecosystem and alliance management at TSMC, shares updates on the foundry’s Open Innovation Platform (OIP) Ecosystem, including TSMC’s vision for enabling AI-driven agentic workflows using the new TSMC AI Design Kit (ADK). **What sparked TSMC’s decision to create the Open Innovation Platform (OIP) Ecosystem, and how has it evolved into the “Leadership Ecosystem” today that is essential to driving the AI expansion?**    As TSMC built out the pure-play foundry model, the OIP ecosystem has democratized the silicon innovation side. Our goals are very simple – how do you streamline the customer design process, how do you accelerate their schedule, and how do you de-risk everything they do to get to a successful tape-out and get to revenue? This is a mission on which we, across our 90+ members in our six alliances, are in complete alignment. [View All](https://www.eetimes.com/category/sponsored-content/) When you look at our 100,000+ IPs and our reference flows, the description of it as a leadership ecosystem is pretty apt. But leadership is not just about doing things today. It’s about looking around the corner and thinking about what we need to do to pre-empt our customers’ needs. This is why we’re supporting our customers with emerging design solutions that we are sharing at our OIP event. We have six startups working on AI-based EDA or enabling AI through their IP to join us. We are expanding our support to enable the entire agentic AI infrastructure to evolve quickly. We also have a new system-level focus that looks beyond the chip and advanced packaging to focus at the rack level, to help ODMs who may not strictly be within our OIP ecosystem, but they are within our customers’ ecosystems. We want to help them and bring our ecosystem to support them. This is how we’ve evolved. But none of this is possible without commitment from our OIP partners, and we are immensely grateful for everything they do for us and our customers. **Energy efficiency is arguably the biggest challenge facing AI expansion today. How is TSMC working with OIP partners to leverage TSMC’s advanced processes, packaging, and COUPE technologies to meet the massive performance and power demands of AI infrastructure?**    I think that’s one thing we can all be in full agreement on – we all need energy efficiency! We look at it from three angles: compute, integration (with memory), and connectivity. For compute, we have DTCO [design technology co-optimization], TSMC’s approach to developing circuit-level IP and process technologies in tandem to deliver the full potential of power, performance, and area (PPA) benefits. But it isn’t just DTCO. DTCO gets the technology ready, but customers should be able to use it, and this is where our ecosystem steps in. We work with our partners to enable these flows, and then to deploy them effectively to customers and support them through that process. Our design services and value chain alliances enable that. As well as digital compute, we also focus on analog, especially since I/O circuits are so energy-critical. We work with our partners from the early stages of PDK development so they can give us feedback, so we can optimise analog PPA. At the system level, we have TSMC-SoIC [system-on-integrated chips, TSMC’s 3D chiplet-stacking technology], but we need to make sure we address all the associated multi-physics effects – thermal, stress. This is where collaboration with the ecosystem is really critical, because we can create the solution, but customers have to design with it. For connectivity, the TSMC COUPE is a game-changing technologY, but you have to optimise the electrical and optical components simultaneously. Electromagnetic extraction at the highest fidelity is critical, while thermal has a very big effect on performance. We have to model that also. Of course, it isn’t only these three areas. We are starting to think about the system: the chip in a package with its connectivity, but in a rack or in an IoT platform – how do we address the design challenges? We are expanding our focus within the ecosystem to deliver on that. **How is AI adoption progressing within design tools themselves? How does TSMC collaborate with EDA partners to integrate AI into design workflows to improve productivity?**    We’re introducing the TSMC AI Design Kit (ADK) to accelerate time-to-market by enabling agentic AI-based design tools and flows built on TSMC technology-specific learning. This initiative boosts digital design productivity by 3x to 5x, and analog/RF design productivity by up to 6x. Today, although our reference flows enable customers to achieve significant results, they often still need to perform manual tuning and workflow optimization based on their unique requirements. Going forward, we expect an agentic framework to accelerate these circuit- and architecture-specific optimizations. Unlike a reference flow with static conditions, the TSMC ADK provides a technology knowledge layer to the agentic framework, enabling it to tune optimally and meet design-specific targets quickly. While we expect to learn a lot as we engage with customers, having this framework in place will allow us to drive progress very quickly. We are very excited about agentic frameworks because of the opportunities for self-learning, self-correcting processes. But this AI journey isn’t new for us – we started several years ago with reinforcement learning in circuit optimization and design space exploration. We work with partners to make sure their tools are ready. For example – for analog, we have a methodology that can help migrate designs between process nodes. Generative AI opened up new possibilities, but with agentic AI, the possibilities are even bigger. We’ll be working with the partners on the TSMC ADK, and we believe this will be the framework that will enable us to support this build-out. **As AI workloads expand from hyperscale data centers to edge computing, how do TSMC’s design solutions address energy efficiency requirements at the edge versus in the cloud?**    Any system deployed at scale will have concerns about performance, energy, and cost, but at the edge, it’s centred around energy and cost. What’s becoming clear is that customer trends [for edge chips] are very clearly heading for the FinFET nodes, to take advantage of the energy benefits. Our ultra-low leakage SRAM allows very low standby power scenarios, so you can add a lot more memory, or you can reduce the voltage, which allows significant dynamic power reduction. *FinFET CAGR is growing steadily in edge applications (Source: TSMC)*  From the ecosystem perspective, we are working with our partners to make sure customers have access to the IP they need, which is tuned for their application and their power and cost envelopes. For example, one of our IP Alliance partners collaborated with our customer, Ambiq, to enable custom IP solutions on TSMC’s N12e process. Through this collaboration, they achieved significant leakage power savings, empowering Ambiq’s edge AI applications. **How is this ecosystem collaboration driving tangible, real-world success for customers? Could you share a recent example where OIP collaboration solved a particularly complex performance or energy efficiency challenge?**  Our collaboration with OIP ecosystem partners has been at our core since day one. Over the last 18 years since its formal establishment, the OIP ecosystem has become the driving force enabling customer innovation—from industry leaders to emerging startups. As our customer keynote speaker at this year’s NA OIP Forum, Greg Dix, VP of Engineering for the ASIC Product Division at Broadcom, showcased how they leverage TSMC’s leading-edge technologies—backed by our robust design ecosystem—to build their latest custom XPU platforms at scale. His presentation highlighted their success in advanced node adoption, heterogeneous multi-die integration, and near-memory co-design. Broadcom is one of many pioneers partnering with us on groundbreaking AI silicon, and it is the collective power of our design ecosystem partners that makes these successes possible. Every day, there is work happening with partners across the board to help customers tackle unprecedented performance and energy-efficiency design challenges, especially amidst the rapid rise of AI. As an example, this year, we collaborated with SK hynix, Samsung Memory, and Micron on the validation of HBM5 CoWoS [Chip-on-Wafer-on-Substrate]. This was a joint project with each partner looking at best practices, aligning DTCO on thermal-mechanical stress challenges. We are also working with our partners, notably our EDA partners, to create reference methodologies and best practices, which we will accelerate with the AI Design Kit. That is critical for customers because it reduces the friction they experience and lowers the barrier to the PPA they are looking for. This year we worked with the three major EDA vendors to organize advanced training for the design services community to level up their expertise, which helps our customers de-risk and reach their targets faster. That had a tangible outcome we are already seeing. Another example is with COUPE, where electrical and optical parts of the system have to be co-optimized within a compact form factor. We also need to pay attention to thermal properties and electromagnetic interference, which have to be modeled carefully. Some partners and customers will present papers on this subject at this year’s OIP Ecosystem Forum Event. **Looking ahead, what’s next for the OIP ecosystem? How will TSMC and its partners continue to collaborate to enable customer design success amidst the accelerated pace of the AI era?**  Each technology transition brings new challenges, but also new opportunities. People are using agentic AI for individual steps (like root cause analysis) and starting to try out orchestrated flows, where multiple agents work with each other and share information during the design cycle. But it’s quickly becoming apparent to our customers that they need quick feedback on the ramifications of their design decisions in terms of timing, parasitics or thermals. Agents work faster, they can work all night, so they can shorten these feedback loops dramatically. This opens up opportunities for innovation around next-generation engines leveraging hardware acceleration to support the rapid turnaround times needed by agentic workflows. There are also opportunities to use customized LLMs to predict design tradeoff choices. Customers ask us whether we have looked at this and how we’re enabling it. So what we have to do going forward will need to be much broader, especially with AI design enablement, where we’re just starting to scratch the surface. The second thing is our system-level focus, which is a new muscle we are now building. Obviously, we have deep expertise on the chip and packaging side, but how do we look at it from a data center point of view, a humanoid robot point of view, or an IoT system point of view? The system is something we are looking at very aggressively, and our ODM partners are aligned on that. I’ll have a progress report on it by this time next year!